Hex String to Unsigned

[rickman]

I seem to be bonking my head against the wall on this one. I have not
found any standard libraries that convert a string of hex digits to an
unsigned variable. I thought it would be easy to write my own, but I'm
having a bit of trouble.

So first, am I reinventing the wheel here? If not, the last issue I'm
having is converting an integer with value of 0 or 1 to a std_logic or
unsigned bit. Any suggestions?

I've been beating on this one for an hour and keep finding different
problems with my approach.

--

Rick C

[Mark Curry]

Rick,

I'm no VHDL power user, but the C function you're looking
for is "strtoul". Googling that, along with "vhdl" turns up
lots of examples.

As I said, I don't know enough VHDL to eval the first few i
clicked, but they look reasonable.

Regards,

Mark

[iamalien]

I think someone might have done this earlier, anyway for converting the integer to binary in vhdl you can use this:
std_logic_vector(to_unsigned(your_integer,required_number_of_bits))
ex, std_logic_vector(to_unsigned(a,8)) (a is signal with integer value less than 256 ofcourse)
And i guess for single bit you could std_logic(to_unsigned(a,1)) (havent used this one, but used the earlier one many times)

[Allan Herriman]

Not standard libraries, but non-standard ones, will do it.
e.g. (Synopsys's) ieee.std_logic_textio has a function called 'hread'
which sounds like it can be made to do what you want. (It reads a line
rather than a string (line is a pointer to a string), and it only works
with std_(u)logic_vector, so you'll need to cast.)

There's a good chance that this is already supported in your simulator.

http://www.csee.umbc.edu/portal/help/VHDL/packages/std_logic_textio.vhd

From STD.textio:
type LINE is access STRING;

Regards,
Allan

[rickman]

Yeah, for some reason I think I was wrapped around the axle and this
isn't hard at all. I can read the hex digits and make an integer, then
convert that to the unsigned easily. I guess I started with the idea of
converting one bit of result at a time and didn't pull back to see
another way of doing it. It doesn't help that I'm working on this just
before bed time... lol.

Thanks for turning on the light. Here is what I ended up with...

function Hex_to_integer (HexChar : character) return natural is
variable temp : natural;
begin
temp := character'pos(HexChar) - character'pos('0');
if temp > 9 then
temp := temp + character'pos('0') + 10 - character'pos('A');
end if;
if temp > 15 then
temp := temp + character'pos('A') + 10 - character'pos('a');
end if;
assert ((temp >= 0) and (temp <= 15))
report "Error converting '" & HexChar & "' as Hex number"
severity error;
return (temp);
end Hex_to_integer;

function to_unsigned (HexDigits : string; DigCnt : positive)
return unsigned is
variable temp : natural := 0;
variable unsgnd : unsigned (DigCnt-1 downto 0) := (others => '0');
begin
for I in HexDigits'LEFT to HexDigits'RIGHT loop
temp := temp + Hex_to_integer (HexDigits (I));
end loop;
return (to_unsigned(temp, DigCnt));
end to_unsigned;


It seems like more hex related functions should be provided. No?

--

Rick C

[iamalien]

Agreed, like many other functions that should have been there by default :D

[rickman]

I missed your post. Yes, HREAD pretty much is what I wanted. I wrote
mine to work with a vector of any length though. HREAD output has to be
a multiple of 4 length.

assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";

I think I should make my own library for hex values. I think I was down
this road some years ago and had a few routines I used, but I didn't
look for them. I should dig them up and consolidate them as a library.

--

Rick C

[Allan Herriman]

Just about every heavy VHDL user I know has their own text processing
library. This points to a problem with the language - it really needed a
standardised, open/free, versatile text processing library in the '90s.

Regards,
Allan

[Jim Lewis]

Hi Rick
Turn on VHDL-2008. It is a testbench after all. Then use ieee.numeric_std.hread. Like your procedure, none of the VHDL-2008 procedures require the length to be a multiple of 4 bits. Hread was also added for std_logic_vector/std_ulogic_vector and signed in the same package in which the types are defined.

Cheers,
Jim