Strange but useful construct: type'(others => '0')
Greg Bell
signal_of_zeros <= std_logic_vector'(others => '0');
This statement will fill signal_of_zeros (a vector) with all zeros. The '()
doesn't look like a function attribute, doesn't look like a type
attribute, and I've never seen this construct used in any other context.
What is it?
Lun Ye
Tim Davis
In article <35l5g2$s...@babbage.ece.uc.edu> Lun Ye,
lu...@vlsilab.ece.uc.edu writes:
>In article <35l0mo$f...@news.cerf.net>, Greg Bell <comq...@nic.cerf.net>
wrote:
>
The name before the tick is a type name. The entire right hand side is an
example of a qualified expression. To quote the LRM'87: "A qualified
expression is used to explicitly state the type, and possibly the
subtype, of an operand that is an expression or an aggregate". Qualified
expressions are used when the type of the aggregate isn't known from the
context.
For this particular case, the type of signal_of_zeros should be known by
the compiler and hence all that is required is:
signal_of_zeros <= (others => '0');
This is a great way to initialize a signal or variable to zeroes or ones
or anything else. The width of signal is determined automagicly (by most
compilers) and hence if you change the width you don't have to go back
and edit all the code. This *idiom* is used quite frequently by VHDL
writers.
Another example of an aggregate is this:
signal_that_is_one <= ( 0=>'1', others => '0');
This gives a signal like "0...0001".
Aggregates are "values" of a particular composite type that specify all
of the elements of that type. (Sorry, the LRM definitions are a little
better). What is a composite type? Arrays and records are composite
types. Each is "composed" of elements. Arrays are homogeneous aggregates
(each element is the same as any other). Records are heterogenous types
(each element may be different then any other). (A bag of OREO cookies is
my favorite example of an array aggregate). Each of the elements in the
aggregate can be specified by positional or named association. Positional
association requires you to name the element *and* provide an expression
to assign to that element. Positional association is just like you use
when you make a function call in C. Each argument has to line up with its
corresponding argument in the function declaration. The OTHERS keyword is
handy because it allows you to specify a few of the elements using named
association then permits the remaining ones to be swept under the carpet
easily. (OTHERS => '0') is just a convenient way of saying make
everything zero.
If you happen to define subtypes for bits in a field within a word then
aggregates like this might be handy:
SUBTYPE alu_op_field IS integer RANGE 3 DOWNTO 0;
SUBTYPE opcode_field IS integer RANGE 5 DOWNTO 4;
SUBTYPE source_field IS integer RANGE 7 DOWNTO 6;
SUBTYPE instruction_type IS bit_vector(7 DOWNTO 0);
SIGNAL instruction : instruction_type;
...
-- Assign constant (perhaps default) values
instruction <= (alu_op_field => '0', opcode_field => '1', source_field
=> '0');
...
-- Assign specific values
instruction(alu_op_field) <= "0010";
instruction(opcode_field) <= "00";
instruction(source_field) <= "10";
This is a way under-utilized feature of the language syntax and
semantics. When used properly it will increase the self documenting
nature of your description significantly.
To summarize a little BNF ...
aggregate ::= (element_association { , element_association } )
element_association ::= [choices => ] expression
choices ::= choice { | choice }
choice ::=
simple_expression
| discrete_range
| element_simple_name
| OTHERS
Have Fun!
...tIM
TimD...@TDCon.com
Holger Veit
See LRM 87 or 93, section 7.3.4 and 7.3.2.2.
--
Dr. Holger Veit | INTERNET: Holge...@gmd.de
| | / GMD-SET German National Research | Phone: (+49) 2241 14 2448
|__| / Center for Computer Science | Fax: (+49) 2241 14 2342
| | / Schloss Birlinghoven | Had a nightmare yesterday:
| |/ 53754 St. Augustin, Germany | My system started up with
| ... Booting vmunix.el ...
David Koontz
A qualified expression assigned to a signal. The more interesting question
is why is the expression qualified?
As expressed in 7.3.4, Qualified Expressions
(the Note)
A qualified expression can be used to state a type explicity when the type
of an aggregate is not known from context.
---
From 7.3.2.2, Array Aggregates
An others choice in an array aggregate (std_logic_vector is an array) can
only appear (number 4.)
As a value expression in an assignment statement, where the target is
a declared object, and the subtype of the target is a constrained
array subtype.
---
Meaning that the array needs to be constrained (Chap 3, Types).
In which case either of the following assignments would work:
library ieee;
use ieee.std_logic_1164.all;
entity foo is
port (
signal signal_of_zeros: out std_logic_vector (11 downto 0)
);
end ;
architecture behave of foo is
begin
signal_of_zeros <= std_logic_vector'(others => '0');
-- or --
signal_of_zeros <= (others => '0');
end behave;
---
The question then becomes can the context be ambiguous? I believe there
is already a requirement to determine if the value ('0') is of the index
type (enumeration literal) of the element type (stand_logic_vector),
(7.3.2.2, Array Aggregates), to determine its numerical (index) value for
assignment.
In other words I don't believe the type mark is required in the assignment
statement.
Wing-Chi Chow
The std_logic_vector'() is a type qualifier. It means that the
expresssion in brackets is of type std_logic_vector.
Wing-Chi
wc...@atitech.ca
Lun Ye
Peter J. Ashenden <pet...@wol.cs.adelaide.edu.au> wrote:
>In article <35l0mo$f...@news.cerf.net>, comq...@nic.cerf.net (Greg Bell) writes:
>specifying an array value by specifying the type of the value and the value of each array element. In the
>example, all elements have the value '0'.
>
>PA
>
>-------------------------------------------------------------------------
>Peter J. Ashenden _--_|\ pet...@cs.adelaide.edu.au
>Dept. Computer Science / \
>University of Adelaide \_.--*_/ Ph: +61 8 303 4477
>SA 5005, Australia v Fax: +61 8 303 4366
>
> http://www.cs.adelaide.edu.au/~petera/
Here is another reply:
=====
From smcwest!west.smc.com!jes...@netcom.com Thu Sep 22 01:24:37 1994
Date: Wed, 21 Sep 94 22:00:53 PDT
From: jes...@west.smc.com (Erik Jessen(Jessen) x2404)
To: lu...@vlsilab.ece.uc.edu
Subject: Re: Strange but useful construct: type'(others => '0')
Newsgroups: comp.lang.vhdl
In-Reply-To: <35l5g2$s...@babbage.ece.uc.edu>
References: <35l0mo$f...@news.cerf.net>
Organization: Standard Microsystems Corp - West Coast
I can't post to comp.lang.vhdl, but I can read it...
The proper syntax is:
signal a : std_logic_vector (5 downto 0) := (others => '0');
This means:
a is a std_logic_vector (it has bits 5 down to 0) and each bit
is initialized to '0'.
The 'others' construct is so that you have an easy way to initialize
large things, without having to repeat the '5 downto 0' part.
As I recall, you can get even more tricky, by assigning some of the
bits to specific values, and set the rest to a default, by using 'others'.
We use this a lot - normally to initialize signals to 'U'.
You can post this if you want...
Erik
=====
and here is one example I used.
=====
SIGNAL memBank : memArray := (
0 => B"00000000",
1 => B"00000000",
16 => B"10000000",
17 => B"11000000",
32 => B"10000000",
33 => B"01000000",
34 => B"11000000",
OTHERS => B"00000000");
==
Lun
--
lu...@thor.ece.uc.edu
--
@@
Electronic Cad Software Account
i am trying to run some VHDL models using QuickVHDL on Falcon V8.4_1.
does qvcom and qvsim require separate licensing because it looks like
QuickVHDL is a part of DA and i guess DA's licensing should hold good for
that also. as of now if i try to run it i get the following message at startup:
// QuickVHDL qvsim v8.4_1.4.2e Jun 15 1994 SunOS 4.1.3
//
// Copyright (c) Mentor Graphics Corporation, 1982-1994, All Rights Reserved.
// UNPUBLISHED, LICENSED SOFTWARE.
// CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
// PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
//
// Copyright (c) Model Technology Incorporated 1990-1994, All Rights Reserved.
//
// License request for qvsim feature failed
// ERROR: License checkout failed
help appreciated !
thanx
- chid
Electronic Cad Software Account
i am a new QuickVHDL user and was trying to run a simple VHDL model using QuickVHDL
on Falcon V8.4_1.
does qvsim and qvcom require separate licenses becos what i felt was that quickVHDL
being a part of DA should be using DA's license, but i get the following message
at startup:
// QuickVHDL qvsim v8.4_1.4.2e Jun 15 1994 SunOS 4.1.3
//
// Copyright (c) Mentor Graphics Corporation, 1982-1994, All Rights Reserved.
// UNPUBLISHED, LICENSED SOFTWARE.
// CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
// PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
//
// Copyright (c) Model Technology Incorporated 1990-1994, All Rights Reserved.
//
// License request for qvsim feature failed
// ERROR: License checkout failed
also a brief outline on the operating procedures would be appreciated
thanx
- chid
Greg Bell
Thanks, Tim and David, for the well researched and complete answers.
Mystery solved. The four VHDL books I check didn't mention OTHERS was
a special keyword for use in aggregate assignments. It sounds like I need
to get myself a copy of the LRM. I suspect the IEEE is the only source
for this in which case I'm sure I'm in for a big task (any tips on
where to easily purchase the LRM?)
In article <1994Sep20.1...@wdl.loral.com> koo...@io.lrmsc.loral.com (David Koontz ) writes:
>A qualified expression assigned to a signal. The more interesting question
>is why is the expression qualified?
Only because a lot of the examples I saw had it this way.
Trivia tidbit for y'all: You can also have an aggregate on the _target_
side of the assignment. So, the following is legal:
SIGNAL a,b,c : std_logic;
BEGIN
(a,b,c) <= '0';
Pretty useful, I'd say!
Rich Hatcher
>
>Thanks, Tim and David, for the well researched and complete answers.
>Mystery solved. The four VHDL books I check didn't mention OTHERS was
>a special keyword for use in aggregate assignments. It sounds like I need
>to get myself a copy of the LRM. I suspect the IEEE is the only source
>for this in which case I'm sure I'm in for a big task (any tips on
>where to easily purchase the LRM?)
To order ANSI/IEEE 1076-1993, try calling ANSI at 212-642-4900.
I think they will take Mastercard or Visa. The last price I've seen
was $67.50 + postage & handling. Also FAX at 212-302-1286
Address: 11 West 42nd Street
New York, NY 10036
Rich Hatcher
>side of the assignment. So, the following is legal:
>
>SIGNAL a,b,c : std_logic;
>BEGIN
>(a,b,c) <= '0';
>
The MTI compiler wouldn't take that, but the following works:
library ieee;
use ieee.std_logic_1164.all;
entity aggr is
end;
architecture test of aggr is
SIGNAL a,b,c : std_logic;
BEGIN
(a,b,c) <= std_logic_vector'("010");
end;
Paul Graham
SIGNAL a,b,c : std_logic;
BEGIN
(a,b,c) <= '0';
Say what? Not unless you think that '0' is of a composite type! You seem
to think that the above construct means
a <= '0'; b <= '0'; c <= '0';
In fact, assignment to an aggregate target effectively splits the source of
the assignment into members of the composite type and assigns these members
to the named objects which appear in the aggregate. So the following would
work:
signal a, b, c : bit;
begin
(a, b, c) <= bit_vector'("010");
and would assign '0' to a, '1' to b, and '0' to c. (The qualified expression
is required to determine the type of the string literal).
Paul
--
Paul Graham gra...@compass-da.com Compass Design Automation, Inc.
(speaking only for myself) "Cekoslovakyalilastiramadiklarimizdanmissiniz."
Joseph Skudlarek
>
> Trivia tidbit for y'all: You can also have an aggregate on the _target_
> side of the assignment. So, the following is legal:
>
> SIGNAL a,b,c : std_logic;
> BEGIN
> (a,b,c) <= '0';
>
>
> Pretty useful, I'd say!
Actually, that needs to be
(a,b,c) <= std_logic_vector'(others =>'0');
^^^^^^^^^^^^^^^^^
as the following program illustrates.
ENTITY e IS
END;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ARCHITECTURE a of e IS
SIGNAL a,b,c : std_logic;
BEGIN
(a,b,c) <= '0';
-- ERROR: foo.v(11): Incompatible types for assignment.
(a,b,c) <= "000";
-- ERROR: foo.v(14): Ambiguous types in assignment: std_ulogic_vector or std_logic_vector
-- ERROR: foo.v(14): Ambiguous types in assignment: bit_vector or std_logic_vector
-- ERROR: foo.v(14): Ambiguous types in assignment: string or std_logic_vector
(a,b,c) <= (others => '0');
-- ERROR: foo.v(19): Ambiguous types in assignment: std_ulogic_vector or std_logic_vector
-- ERROR: foo.v(19): Ambiguous types in assignment: bit_vector or std_logic_vector
-- ERROR: foo.v(19): Ambiguous types in assignment: string or std_logic_vector
(a,b,c) <= (others => std_logic'('0'));
-- ERROR: foo.v(24): Ambiguous types in assignment: std_ulogic_vector or std_logic_vector
-- ERROR: foo.v(24): Ambiguous types in assignment: bit_vector or std_logic_vector
-- ERROR: foo.v(24): Ambiguous types in assignment: string or std_logic_vector
(a,b,c) <= std_logic_vector'("000");
(a,b,c) <= std_logic_vector'(others =>'0');
END;
/Jskud
--
----------------------------------------------------------------------------
Joseph P. Skudlarek Mentor Graphics 8005 SW Boeckman Rd Wilsonville OR 97070
Js...@wv.MentorG.com Joseph_S...@MentorG.com 503/685-1576@work
Andy Rushton
> Where the heck does this construct come from:
>
> signal_of_zeros <= std_logic_vector'(others => '0');
>
This is a qualified expression being applied to an aggregate. There are
therefore two parts to it. The (others => '0') part is the aggregate and
defines a value for an array, typically to initialise the array or give
it a constatnt value (although not constrained to this). The "others"
keyword says "make the aggregate as big as the array its being assigned
to and fill it with '0's"
The problem with aggregates is that they can be ambiguous. In this case,
is the aggregate representing a string, a bit_vector, a
std_logic_vector, a numeric_bit.signed, etc...
Usually the type of an aggregate is clear from its context - for
example:
signal a : bit_vector (7 downto 0);
...
begin
a <= (others => '0');
However, there are cases where the type of the aggregate cannot be
ascertained, and in these cases it is necessary to give the analyser
more information on the type of the aggregate using type qualification
(for a less clear description, see LRM 7.3.4). This is what you give
above.
The same problem can also occur with ambiguous string values and these
can also be solved with type qualification:
bit_vector'("0000")
Final warning: don't confuse this with type conversion, they are not the
same thing:
bit_vector("0000");
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- --
Andy Rushton #8-) email a...@transeda.demon.co.uk
TransEDA Limited tel. +44-703-255118
Pilgrims Close fax. +44-703-270278
Chandlers Ford time WET
Hants SO53 3ST, UK
assert opinion report "mine, not TransEDA's" severity cheerful;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- --
Paul J Menchini - Menchini and Associates
: Thanks, Tim and David, for the well researched and complete answers.
: Mystery solved. The four VHDL books I check didn't mention OTHERS was
: a special keyword for use in aggregate assignments. It sounds like I need
: to get myself a copy of the LRM. I suspect the IEEE is the only source
: for this in which case I'm sure I'm in for a big task (any tips on
: where to easily purchase the LRM?)
See my posting of a few minutes ago on another thread.
: Trivia tidbit for y'all: You can also have an aggregate on the _target_
: side of the assignment. So, the following is legal:
: SIGNAL a,b,c : std_logic;
: BEGIN
: (a,b,c) <= '0';
: Pretty useful, I'd say!
Yes, but not quite right. The left and right sides of the assignment have
to be of the same type, and if an array, have to also have the same number
of elements.
So, two examples of correct assignments in the above example are:
(a,b,c) <= three_bit'("000");
and
(a,b,c) <= three_bit'('0', '0', '0');
Qualification of the RHS is necessary since the type of an aggregate or of
a string "must be determinable from context." In English, the string can
be of any type that is a one-dimensional array whose element type is a
character type, while the aggregate could be any one-dimensional array type
or any record type.
BTW, here's a possible definition of "three_bit."
type three_bit is bit_vector (2 downto 0);
--Paul
--
Paul Menchini |me...@mercury.interpath.net|"Problems worthy of attack
Menchini & Associates| voice: 919-990-9506 |prove their worth by
2 Davis Dr./POB 13036| pager: 800-306-8494 |hitting back."
RTP, NC 27709-3036 | fax: 919-990-9507 | -- Piet Hein