wait for 0, the delta cycle.
Kees Goossens
Three simple short questions:
- Is "wait for 0ns" legal VHDL?
- If so, does anyone use it?
- Do you consider the delta cycle anything else than a computational
(simulator) artifact? (In other words, it does not model real time.)
Thanks.
Kees
--
Kees Goossens <k...@dsi.uniroma1.it> http://www.dcs.ed.ac.uk/staff/kgg/
Dip. di Scienze dell'Informazione, Universita di Roma "La Sapienza", Italy
A sciencia n\~ao trata das cousas que sam somente ymaginarias falsas ou
ympossiveis: mas das certas e verdadeiras -- Pedro Nunes, c.1549
Charles Shelor
>Hi all.
>
>Three simple short questions:
>
>- Is "wait for 0ns" legal VHDL?
>- If so, does anyone use it?
>- Do you consider the delta cycle anything else than a computational
> (simulator) artifact? (In other words, it does not model real time.)
>
>Thanks.
>
>Kees
>--
wait for 0 ns; -- will pause for a delta cycle and is perfectly legal.
It is used ''frequently'' to allow just assigned signal values to propagate
through the simulation.
It is not just an artifact. It is required to handle concurrency and still
get deterministic results from different VHDL simulators. All event driven
concurrent simulations have something similar to delta cycles although it
might not be 'visible' to anyone other than the simulation programmers. VHDL
made it explicit to ensure every VHDL simulator produced the same results
for the same input code.
Charles F. Shelor
SHELOR ENGINEERING VHDL Training, Consulting, and models
3308 Hollow Creek Rd (817) 467-9367
Arlington, TX 76017-5346 cfsh...@acm.org
Lun Ye
>Hi all.
>
>Three simple short questions:
>
>- Is "wait for 0ns" legal VHDL?
no. "wait for 0 ns;" is.
>- If so, does anyone use it?
yes. i just saw an example posted here.
>- Do you consider the delta cycle anything else than a computational
> (simulator) artifact? (In other words, it does not model real time.)
true. it is a computational(simulator) artifact. a discrete event simulator for
VHDL without delta cycles will be much much faster -- only if it is possible to
build such a simulator.
>
>Thanks.
>
>Kees
>--
>Kees Goossens <k...@dsi.uniroma1.it> http://www.dcs.ed.ac.uk/staff/kgg/
>Dip. di Scienze dell'Informazione, Universita di Roma "La Sapienza", Italy
>A sciencia n\~ao trata das cousas que sam somente ymaginarias falsas ou
>ympossiveis: mas das certas e verdadeiras -- Pedro Nunes, c.1549
--
#include <std_disclaimers>
Yves DURAND
> Hi all.
>
> Three simple short questions:
>
> - Is "wait for 0ns" legal VHDL?
yes, but you should write
wait for 0 ns;
(white space added)
> - If so, does anyone use it?
you can use it when you want to force the scheduler to update
your signals. example:
A <= 1;
-- driver of A gets an 1
Wait for 0 ns;
-- effective value of A updated
B <= A; -- here A=1
this may be useful in some cases, when you translate from another
language or when you want to force the calling of some ugly
resolution function...
> - Do you consider the delta cycle anything else than a computational
> (simulator) artifact? (In other words, it does not model real time.)
this word "delta cycle" is a little confusing. I prefer to talk about
one pass of the scheduler algorithm, which updates the signals.( When
you think that way, "real time" becomes an artifact also :-)
>
> Thanks.
>
> Kees
> --
> Kees Goossens <k...@dsi.uniroma1.it> http://www.dcs.ed.ac.uk/staff/kgg/
> Dip. di Scienze dell'Informazione, Universita di Roma "La Sapienza", Italy
> A sciencia n\~ao trata das cousas que sam somente ymaginarias falsas ou
> ympossiveis: mas das certas e verdadeiras -- Pedro Nunes, c.1549
does this apply also to the LRM ??
--
_________________________ __@
Yves DURAND ... _`\<,
HEWLETT-PACKARD (*)/ (*)
Grenoble Networks Division Lab Email: Yves_...@grenoble.hp.com
Naresh Soni
If anyone has a VHDL Model for UART, please let me know. This UART can be generic
UART (need not be a fancy one).
My email address: nar...@aluxs.att.com
Thanks,
Naresh Soni