Component Declaration:
component <component_name>
generic (
my_generic : integer := 1;
<other generics>...
);
port (
<port_name> : <mode> <type>;
<other ports>...
);
end component;
Component Instantiation:
<instance_name> : <component_name>
generic map (
my_generic => 2,
<other generics>...
)
port map (
<port_name> => <signal_name>,
<other ports>...
);
Thanks,
Marco
Component Instantiation:
<instance_name> : <component_name>
generic map (
--**** my_generic => 2,
The value you specify in the declaration (my_generic : integer := 1) is the
default value.
The value you specify in the instantiation (generic map my_generic => 2) is
the actual value.
If no actual value is specified, the default value is used. If no actual
value is specified and no default value is specified either, then the
instantiation is an error.
Cheers,
-Ben-
> If no actual value is specified, the default value is used. If no actual
> value is specified and no default value is specified either, then the
> instantiation is an error.
Let me add: This is a common a pitfall during synthesis. If you
synthesize the subcomponent, the default value will be used, if you
don't specify an actual value to the synthesis tool. If you forget it,
your synthesis tool uses the default value and your testbench a
different actual one.
Ralf
If you have a component as in your example
component <component_name>
generic (
my_generic : integer := 1;
<other generics>...
);
port (
<port_name> : <mode> <type>;
<other ports>...
);
end component;
and you synthesize this component alone without giving a different
actual value to the generic my_generic, the synthesis tool will
synthesize with the default value which is 1.
Now, if you simulate your netlist inside your design making an
instantiation as in your example
Component Instantiation:
<instance_name> : <component_name>
generic map (
my_generic => 2,
<other generics>...
)
port map (
<port_name> => <signal_name>,
<other ports>...
);
then this will lead to wrong behavior, because the instantiation assumes
my_generic to be 2, but the netlist was synthesized with my_generic=1.
The netlist is fixed.
This pitfall is not a special behavior, but simply something, that can
be easily forgotten.
Ralf
I think if the entity declaration has a default value, it may take
that, in the absense of either a default declaration on the component,
or an actual value in the generic map of the instance.
BTW, most tools (synpsys still has a few troubles with it) take entity
instantiations, obviating the need for component declarations,
configurations, default bindings, etc.
u1: entity entity_name(architecture_name)
generic_map(...
This has been a feature of vhdl since 1993!
Andy