How to access individual bits of std_logic_vector

[Daku]

Could some VHDL guru please help ? I am using the Alliance 5.0 tool. I
have:

ARCHITECTURE dataflow_view OF ram IS
SUBTYPE INDX IS std_logic_vector(0 to 31);
SIGNAL index : INDX;
-- Some other declarations
Now, inside a process, I wish to examine the content of each location
in index - if it is '0'
do something as in:

BEGIN

RAM_0 : PROCESS( WEB )
VARIABLE cnt : INTEGER RANGE 0 TO 31;

BEGIN
IF (WEB='1' AND WEB'EVENT )
THEN IF (REB='0') THEN
IF (index(0) = '0') THEN
cnt := 0;
END IF;
--memory( CONV_INTEGER( A ) ) <= INN;
END IF;
END IF;
END PROCESS RAM_0;

I am getting an error message as:
--> Run VHDL Compiler
--> Compile file ram
parse 118 ERROR size of atom index_idx_0 should be static

Any hints, suggestions would be of immense help. Thanks in advance for
your help.

[Tricky]

You dont make much sense, as there isnt anything wrong you the code
you've posted. Are you trying to find the first index of a
std_logic_vector that is '0'? or every index? What do you want to do
when you've discovered one bit is '0'?

[Daku]

On Nov 19, 1:50 pm, Tricky <trickyh...@gmail.com> wrote:

I want to iterate over each element of
std_logic_vector, and depending on whether it is
'1' or '0', do something else.

[KJ]

On Nov 19, 5:38 am, Daku <dakup...@gmail.com> wrote:
> On Nov 19, 1:50 pm, Tricky <trickyh...@gmail.com> wrote:
>
> I want to iterate over each element of
> std_logic_vector, and depending on whether it is
> '1' or '0', do something else.
>

You would use a for loop to iterate over the range of a vector and an
if statement to do conditional logic. An example below

process(Clock)
begin
if rising_edge(Clock) then
for Index in My_Vec'range loop
if My_Vec(Index) = '1' then
-- Do something
else
-- Do something else
end if;
end loop;
end if;
end process;

Kevin Jennings

[Daku]

I fully agree/understand and have tried out what you have said below,
but I am getting an error
message that does not make much sense to me. I
am using the Alliance 5.0 toolset.
I have :

ENTITY ram IS
port ( A : in std_logic_vector(0 to 31);
CEB : in std_logic;
WEB : in std_logic;
REB : in std_logic;
INN : in std_logic_vector(0 to 31);
OUTT : out std_logic_vector(0 to 31)
);
END ram;

ARCHITECTURE dataflow_view OF ram IS
SUBTYPE INDX IS std_logic_vector(0 to 31);
SIGNAL index : INDX;

--Some other declarations

BEGIN

RAM_0 : PROCESS( WEB )
VARIABLE cnt : INTEGER RANGE 0 TO 31;

BEGIN
IF (WEB='1' AND WEB'EVENT )
THEN IF (REB='0') THEN
IF (index(0) = '0') THEN
cnt := 0;
END IF;

memory( CONV_INTEGER( A ) ) <= INN;
END IF;
END IF;
END PROCESS RAM_0;

-- Some other processes
The compile time error message is:

--> Run VHDL Compiler
--> Compile file ram
parse 118 ERROR size of atom index_idx_0 should be static

Looks like it does not like : IF (index(0) = '0')

Could someone please point out what exactly is the
problem ?

[Mark McDougall]

Daku wrote:

> Could someone please point out what exactly is the
> problem ?

As Kevin said, looks fine without actually trying it. Maybe your tools are
just crap? I've had very similar errors in ModelSim that just don't make
sense either... though mainly involving ranges specified with generics...

BTW your VHDL coding style looks like you're a software programmer. I'd
suggest you lose the brackets around the 'if' condition...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

[Alan Fitch]

Hi Daku,
I think, as Mark says, the problem is the simulator. I had a look at
the Alliance toolset, and it seems to have two simulators. For one,
Asimut, it says

"ASIMUT is not a powerfull VHDL simulator compared to industrial one. It
is used at LIP6 laboratory only for teaching purposes or small research
projets. For example it doesn't take benefit of vectorized expressions,
during compilation it splits them to an equivalent set of bits. During
the simulation it interprets all boolean expressions, it is not
effecient and it is very CPU time consuming compared to compiled and run
methods. Finally, the VHDL subset it accepts is not standard and is very
small. For example only boolean operators are supported, and only two
VHDL types can be used (bit and bit vectors). "

For the other, VASY, it says

"The VHDL compiler of VASY is very permissive and it doesn't verify the
correctness of the input description (according to the VHDL standard
reference manual). Another problem is that enumerate types are encoded
and they disappear in the resulting VHDL description. "

VASY is also described as "It loads VHDL behavioral or structural
descriptions (written according to the Synopsys VHDL subset)." whatever
that means.

So I would say "get a better simulator",

Various FPGA vendors have free toolsets that contain VHDL simulators.

regards
Alan

>
> On Nov 19, 5:13 pm, KJ <kkjenni...@sbcglobal.net> wrote:
>
>> You would use a for loop to iterate over the range of a vector and an
>> if statement to do conditional logic. An example below
>>
>> process(Clock)
>> begin
>> if rising_edge(Clock) then
>> for Index in My_Vec'range loop
>> if My_Vec(Index) = '1' then
>> -- Do something
>> else
>> -- Do something else
>> end if;
>> end loop;
>> end if;
>> end process;
>>
>> Kevin Jennings
>

--
Alan Fitch
Senior Consultant

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[Daku]

I thank each one of you for your feedback. The really funny thing
is that if I have :

ARCHITECTURE dataflow_view OF ram IS

SIGNAL index : std_logic_vector (0 to 31);

Instead of :

ARCHITECTURE dataflow_view OF ram IS
SUBTYPE INDX IS std_logic_vector(0 to 31);
SIGNAL index : INDX;

Then the following compiles without a murmur of protest:

RAM_0 : PROCESS( WEB )
VARIABLE cnt : INTEGER RANGE 0 TO 31;

BEGIN
IF WEB='1' AND WEB'EVENT
THEN IF REB='0' THEN
FOR I IN index'RANGE LOOP
IF index(I) = '0' THEN
cnt := I;
EXIT;
END IF;
END LOOP;

memory( CONV_INTEGER( A ) ) <= INN;

So right now I am hunting for a good VHDL simulator/verifier.
Thank you all.

> Doulos – Developing Design Know-how

> VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project
> Services
>
> Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24
> 1AW, UK

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