Question about using signal as actual in generic map
mkoch
entity ent is
generic(g: integer);
end;
architecture a of ent is
begin
end;
entity top is end;
architecture a of top is
signal s1,s2,s3: integer := 3;
component comp is
generic(g: integer);
end component;
for u1: comp use entity work.ent(a) generic map(g=>s2);
begin
u1: comp generic map(g=>s1);
u2: entity work.ent(a) generic map(g=>s1);
end;
configuration cfg of top is
for a
for u1: comp generic map(g=>s3);
end for;
end for;
end configuration;
Regards,
MK.
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Before you buy.
e...@riverside-machines.com.nospam
>The question is: this is legal or not?
<snipped>
I think that the intent of the language is clear: the formal is a
constant, and it should be associated with a globally static
expression, and, since a signal name isn't a globally static
expression, then it should be illegal.
However, I don't think that the LRM actually says this. If you have a
*port* that's of class constant, then it does explicitly say that the
corresponding actual should be a globally static expression. I haven't
seen anything about generics, though.
In any event, it won't work even if it's allowed. The generics are
evaluated during elaboration, and the actual signal in your example
won't have a value at this time.
Evan
Mike Treseler
>
> The question is: this is legal or not?
------------------------------------
Modelsim says not:
ERROR: sig_test.vhd(18):
Actual expression for generic "g" cannot reference a signal.
-- mike.treseler at flukenetworks dot com
me...@mench.com
article <8tr8g1$jio$1...@nnrp1.deja.com>:
> The question is: this is legal or not?
It's not. Signals don't have any values during static elaboration.
Paul
--
Paul Menchini | "A little beyond perception's reach / I sometimes
Menchini & Associates | believe I see / That life is two locked boxes,
www.mench.com | each / Containing the other's key.
| --Piet Hein
mkoch
Yes - I try that with ModelSim - but tell me: why only one case is
treated as error, while two others not? When I change error line(18)
compilation passed without errors...
rgs,
mkoch
If - as You said - signals don't have values during elaboration, please
explain this example:
----------------------------------------
entity ent is
port(p: inout integer := 5);
end;
architecture a of ent is begin end;
entity top is end;
architecture a of top is
signal s: integer := 3;
function fconv(input: integer) return integer is
begin
report integer'image(input);
return input;
end;
begin
u: entity work.ent(a) port map(fconv(p)=>fconv(s));
end;
----------------------------------------
Output from ModelSim while initialization, but before simulation:
# ** Note: 3
# Time: 0 ps Iteration: 0 Region: /top/u
# ** Note: 5
# Time: -9223372036854775807 ps Iteration: 0 Signal: /top/s
# ** Note: 5
# Time: -9223372036854775807 ps Iteration: 0 Region: /top
mkoch
In LRM, I found statement about actual as globally static expression,
but this is relate to port map (not generic map). For actual in generic
map I found only this: actual must be expression.
What is my problem: in my example, are 3 different generic maps with
actual as signal - but ModelSim only one of them treat as error - why?
I think this is a bug, but I don't know, that bug is:
1. Error reporting for one case, or
2. Missing error reporting for two other cases.
Srinivasan Venkataramanan
In article <8tto21$m11$1...@nnrp1.deja.com>,
mkoch <marek...@usa.net> wrote:
> In article <8tsma0$eq3$1...@mench.mench.com>,
> me...@mench.com wrote:
> > On Thu, 02 Nov 2000 08:26:45 GMT, mkoch <marek...@usa.net> wrote
in
> > article <8tr8g1$jio$1...@nnrp1.deja.com>:
> >
> > > The question is: this is legal or not?
> >
> > It's not. Signals don't have any values during static elaboration.
> >
> > Paul
> >
> If - as You said - signals don't have values during elaboration,
please
> explain this example:
>
> ----------------------------------------
> entity ent is
> port(p: inout integer := 5);
> end;
>
> architecture a of ent is begin end;
>
> entity top is end;
>
> architecture a of top is
> signal s: integer := 3;
> function fconv(input: integer) return integer is
> begin
> report integer'image(input);
> return input;
> end;
> begin
> u: entity work.ent(a) port map(fconv(p)=>fconv(s));
> end;
> ----------------------------------------
I guess you meant "generic map" instead of port map (as that's what
is relevant to this thread). If so your code would look like
entity ent is
generic(p: integer := 5);
end;
architecture a of ent is begin end;
entity top is end;
architecture a of top is
signal s: integer := 3;
function fconv(input: integer) return integer is
begin
report integer'image(input);
return input;
end;
begin
u: entity work.ent(a) generic map(fconv(p)=>fconv(s));
end;
----------------------------------------
As far as my understanding goes this should NOT compile/elaborate,
BUT Modelsim (version 5.3b) does compile this fine - guess it is a bug.
VHDLSimli from Symphony doesn't compile this.
This is b'cos as already said "the actual in the genric map should be
globally static" and a "Pure function call with a non-globally static
arguments is NOT globally static" (In your case the function fconv has
the signal "s" as its argument - which is not globally static - that
makes the function call itself as GLOBALLY NON-STATIC).
Hope this helps,
Regards,
Srini
--
Srinivasan Venkataramanan
ASIC Design Engineer
Chennai, India
e...@riverside-machines.com.nospam
I wouldn't worry about this. I ran your code through an old ModelSim
(4.7) and it didn't report any errors at all. I don't think this can
be classified as a bug, since I don't believe you can point to a
section of the LRM that says that this is illegal. However, it's
clearly not going to work (see para 3 of section 12 - nets should be
initialised *after* elaboration), so ModelSim is free to say whatever
it wants about the code. And, even if it does "work" for a particular
version of ModelSim, then it's certainly not portable.
Evan
me...@mench.com
article <8tto21$m11$1...@nnrp1.deja.com>:
> entity top is end;
Tool that doesn't implement the LRM?