Read and write signal in same process
Ivan Johansen
I am new to VHDL and I have a problem resetting a signal after reading
it. I am trying to copy a signal sig_a into another signal sig_b and
resetting sig_a. I have a process with this:
if clk'event and clk='1' then
sig_b <= sig_a;
sig_a <= '0';
end if;
The simulator ModelSim shows both sig_a and sig_b as 'X' afterwards.
Is this not possible? How do I reset a signal after moving it?
Ivan Johansen
Allan Herriman
wrote:
It is likely that sig_a is 'X' because it has a driver in another
process, and 'X' is produced when the drivers drive different levels
('0' from this process, '1' from another process). Search your code
for other assignments to sig_a (i.e. sig_a <= something;). Ensure
that there are assignments to sig_a in only this process.
Your simulator has a command that displays drivers for a signal. Use
it to locate the source of this problem.
>I am new to VHDL
The lesson for today is that assignments to signals in VHDL are *not*
like assignments to variables in other languages.
http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#drivers
Regards,
Allan.
Jussi Lähteenmäki
It shouldnt produce X's, but, on the other hand, the code below makes very
little sense. You have a constant driver '0' on sig_a (ie. it's a small
ROM memory unit) and then you want to drive the output of sig_a register
into the input of sig_b register. This happen's on every rising edge of
the clock, therefore, being pretty much useless. Try something like:
if clk'event and clk='1' then
if control_signal = '1' then
sig_b <= sig_a;
sig_a <= '0';
end if;
end if;
often it helps to really describe the problem more closely,
juza
: I am new to VHDL and I have a problem resetting a signal after reading
: Ivan Johansen
--
Juza
Ivan Johansen
> It is likely that sig_a is 'X' because it has a driver in another
> process, and 'X' is produced when the drivers drive different levels
> ('0' from this process, '1' from another process). Search your code
> for other assignments to sig_a (i.e. sig_a <= something;). Ensure
> that there are assignments to sig_a in only this process.
>
> Your simulator has a command that displays drivers for a signal. Use
> it to locate the source of this problem.
So it is possible to reset a signal after assigning from it. I will
start looking for other drivers of the signal. Thanks for the hint.
> The lesson for today is that assignments to signals in VHDL are *not*
> like assignments to variables in other languages.
> http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#drivers
Thank you for the link. I will take a look at it.
Ivan Johansen
Ivan Johansen
> It shouldnt produce X's, but, on the other hand, the code below makes very
> little sense. You have a constant driver '0' on sig_a (ie. it's a small
> ROM memory unit) and then you want to drive the output of sig_a register
> into the input of sig_b register. This happen's on every rising edge of
> the clock, therefore, being pretty much useless. Try something like:
>
> if clk'event and clk='1' then
> if control_signal = '1' then
> sig_b <= sig_a;
> sig_a <= '0';
> end if;
> end if;
This is just a small example to illustrate the problem. The actual code
is
much more complex and I don't assign to sig_a on each clock.
A friend of mine insisted that it was not possible to assign to sig_a
when
it has just been assigned from. I take it from your response that it is
possible. Thank you.
Ivan Johansen