vhdl #ifdef?

[John]

Is there an equivalent to the C style #ifdef in vhdl? Sometimes I have
some vhdl code that I don't want to compile for various reasons
(not working yet, a new untested idea, etc.) and I would like to just
#ifdef it out and use something else in it's place, but I don't know how
to do that. I'm using Synplify and Modelsim. Commenting out a bunch
of lines is cumbersome.

Thanks for any suggestions.

[Harlin Hamilton Jr.]

Usually you can block comment with
-- <tool> <command>_off
-- <tool> <command>_on

An example would be:
-- synopsys synthesis_off
<commented code>
-- synopsys synthesis_on

I think that Synplicity honors the above synopsys
sythesis directives. I also think that they have
some of their own. However, I do not think that
VHDL itself supports compile driven directives.

Hope that helps,
Harlin!

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[nullandvoid]

afaik the closest thing VHDL has to #ifdef is the use of boolean
generics. you can create a generic to turn things on or off for
simulation. i'm sure you can do the same thing for synthesis
although i haven't tried doing so. here's an example:

entity tb is
generic (exec : boolean := false); -- default is not to execute
end entity tb;

architecture bhv of tb is
begin
p1 : process
begin
-- if exec is true ...
if (exec) then
-- ... do what's inside the if
report "Executing Code!";
end if;
end process p1;
end architecture bhv;

compile as you normally would. then when you load your design
into ModelSim, use the -g option to turn on your generic. for
the example above, the command would look like:

vsim tb -gexec=true

(notice how the generic immediately follows the -g)

if the generic is not in the top level, or you want to specify
that all generics of the same name take a particular value, use
the -G option. syntax is same as the example above.

if you use the gui to load your design, there's a tab where you
can specify the generic value (can't remember the name although
i believe it's VHDL Options).

perhaps someone else will post about how to use generics for
synthesis.

ciao,

NaV

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[Ray Andraka]

Why not use the synthesis_on and synthesis_off pragmas?

nullandvoid wrote:

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[nullandvoid]

In article <3921BB4E...@andraka.com>, Ray Andraka

<r...@andraka.com> wrote:
>
>Why not use the synthesis_on and synthesis_off pragmas?
>

yes, synthesis pragmas/directives are probably the only way to
solve the problem of stepping over text for synthesis. the
experts will probably say that, from a synthesis view, generics
should only be used to parameterize some bounds on a design.
for instance, one designs a RAM and uses generics to create RAMs
of varying widths and depths.

however, i'm not familiar with any directives for compiling for
simulation. also, in the spirit of #ifdef's (which are set at
compile time), generics are set at run time and don't require
editing the code to get a different behavior. to remove or add
pragmas you'll have to modify the code. although, deleting or
adding a few lines is much easier than having to comment many
(hundreds?) lines of code. unless you have an awesome editor.
but then that's an entirely different thread. 8)

[Peter Close]

You could also choose to use boolean constants to control instantiation of
alternative components...

constant ENABLE_X : boolean := true;
...
G1: if ENABLE generate
C1: comp1 generic map (...) port map (...);
end generate;

Peter

John <jss...@hotmail.com> wrote in message
news:219DB28AF719D31180CE00609774020D03B3C3D2@US1-NNTP...