Constants in a configuration file
Anthony Rouaux
i d like to know if it is possible to include in a vhdl file an other
file(like a package) wich contains constants declarations.
I want to do this to configure my design an to change several parameters
between two synthese.
Does anyone can help me?
Thanks a lot
Anthony
Jonathan Bromley
Anthony Rouaux <anthony...@oreka.com> writes
>Hi all,
>i d like to know if it is possible to include in a vhdl file an other
>file(like a package) wich contains constants declarations.
>I want to do this to configure my design an to change several parameters
>between two synthese.
There is no "textual include" mechanism in VHDL, although of course
you could easily do it using an external preprocessor.
It's far better to create a package that declares some constants.
Even better, use deferred constants like this:
package MyConstants is
constant width: integer; -- N.B. : No value given here!
end;
and then in a SEPARATE FILE, so you can compile it separately:
package body MyConstants is
constant width: integer := 15; -- Change this as needed
end;
Using the constants is straightforward:
use work.MyConstants.all;
Now when you are simulating, the only source file that you must
recompile is the package body; everything else will be built
correctly at elaboration.
Synthesis tools will probably re-read every source file for each
synthesis run.
We discuss this, and a bunch of other possible approaches to
configuration management, in our Expert VHDL course...
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: jonathan...@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
**********************************
** Developing design know-how **
**********************************
This e-mail and any attachments are confidential and Doulos Ltd. reserves
all rights of privilege in respect thereof. It is intended for the use of
the addressee only. If you are not the intended recipient please delete it
from your system, any use, disclosure, or copying of this document is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Allan Herriman
I just did this...
When you have a lot of contants that must be altered at the same time,
it may be convenient to access them through arrays, with another
constant as the index.
E.g.
type t_type_of_design is (type_1, type_2, type_3);
-- this single constant drives everything
-- (It can be deferred, as Jonathan suggested)
constant DESIGN : t_type_of_design := type_1;
type t_integer_array is array (t_type_of_design range <>) of
integer;
constant CONST_1_ARRAY : t_msg_integer_array := (
type_1 => 42,
type_2 => 69,
type_3 => 666
);
constant CONST_1 : integer := CONST_1_ARRAY(DESIGN);
constant CONST_2_ARRAY : t_msg_integer_array := (
type_1 => 255,
type_2 => 127,
type_3 => 31
);
constant CONST_2 : integer := CONST_2_ARRAY(DESIGN);
... and so on
This is synthesisable (tested in Synplify 6.2.3). Modelsim and Simili
liked it too.
Regards,
Allan.
Allan Herriman
allan_herrim...@agilent.com (Allan Herriman) wrote:
> type t_type_of_design is (type_1, type_2, type_3);
>
> -- this single constant drives everything
> -- (It can be deferred, as Jonathan suggested)
When I tried using a deferred constant, Modelsim said "illegal use of
deferred constant" so I'll know not to try that again.
Allan.
Jonathan Bromley
<allan_herrim...@agilent.com> writes
>When I tried using a deferred constant, Modelsim said "illegal use of
>deferred constant" so I'll know not to try that again.
That's a new one on me. What was the context?
I can think of two reasons from what I understand of the LRM:
1) you tried to use the deferred constant somewhere else in the
same package, or in the package body but before the
full declaration of the deferred constant;
2) you tried to use it somewhere a locally static value is needed.
I've always thought deferred constants were rather cool, and
invariably recommend them to my troops before they go into battle :-)
VhdlCohen
and not locally static. At one time, ModelSIm interpreted them as locally
static, which is incorrect. I don't know if they fixed that yet (anyone
knows?). Rationale then (from MTI) was that they were implementing the
"intent" of the language, rather than the letter of "LRM" law.
Globally static objects have restrictions in the use of the CASE satatements.
Personally, I think that objects of a constant array should be locally static,
but per lrm'93 they are not because it is not one of the 8 or so conditions
that define what is a locally static.
--------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdl...@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------
Allan Herriman
<Jonathan...@doulos.com> wrote:
>In article <3c46f55c...@netnews.agilent.com>, Allan Herriman
><allan_herrim...@agilent.com> writes
>
>>When I tried using a deferred constant, Modelsim said "illegal use of
>>deferred constant" so I'll know not to try that again.
>
>That's a new one on me. What was the context?
>
>I can think of two reasons from what I understand of the LRM:
>
>1) you tried to use the deferred constant somewhere else in the
> same package,
It was this one. I would have needed to make the other constants
deferred too.
Thanks,
Allan.
jacky Renaux
Use a package file this is easy and very usefull
I think it is a good practice to store in one single
file , all designs constants . for
team based design , this file will be shared by all
design change : instead to browse all files , only
one has to be checked
later change : you dont have to reread all the designs
file to undestand which constant has to be modified
global constant : a package file is the best way
does someone disagree?
following is an exemple
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package my_package is
constant large : integer := 10;
subtype pix_width is std_logic_vector(7 downto 0);
end my_package;
package body my_package is
end my_package;
---------- design files
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.my_package.ALL;
entity My_entity is
Port ( clka,clkb: std_logic;
data_in : in pix_width;
data_out : out (std_logic_vector(large-1 downto 0);
etc......
hope it will help
--
Use our news server 'news.foorum.com' from anywhere.
More details at: http://nnrpinfo.go.foorum.com/
Srinivasan Venkataramanan
>
> Synthesis tools will probably re-read every source file for each
> synthesis run.
>
IIRC Synthesis tools don't support deferred constants, atleast
DC's document says it explicitly in Appendix-C. Have you used them for
Synthesis?
> We discuss this, and a bunch of other possible approaches to
> configuration management, in our Expert VHDL course...
Perhaps meant more for Behavioural modeling & Verification?
Thanks,
Srinivasan
--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India, Visit: http://www.simputer.org)
"I don't Speak for Intel"
VhdlCohen
> IIRC Synthesis tools don't support deferred constants, atleast
>DC's document says it explicitly in Appendix-C. Have you used them for
>Synthesis?
>
SYnplicity Synplify DOES support deferred constants, and I believe tat the
trend for to vendors is to do so Below is code test on Synplify Pro
package MyConstants is
constant width: integer; -- N.B. : No value given here!
end;
package body MyConstants is
constant width: integer := 15; -- Change this as needed
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.MyConstants.all;
entity X is
port (
a : in std_logic_vector(width-1 downto 0);
c : out std_logic_vector(width-1 downto 0));
end entity X;
architecture rtl of X is
begin -- architecture rtl
c <= not a;
end architecture rtl;
--------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdl...@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------
.
ham...@cloud.net.au
> IIRC Synthesis tools don't support deferred constants, atleast
> DC's document says it explicitly in Appendix-C. Have you used them for
> Synthesis?
I've used them with Synplify Pro 6.2.4 and it worked OK. I had a couple
of constants which were the results of functions declared in the package
body, so they had to be deferred.
Then I used the deferred constants to set the size of some
std_logic_vectors in other source files.
Hamish
--
Hamish Moffatt VK3SB <ham...@debian.org> <ham...@cloud.net.au>