AHDL - VHDL comparision
Thai Hoa Vo
Altera suggests to use AHDL instead of VHDL. Does it mean that AHDL
give a better optimization in term of resource and performance ?
Thank you.
Jan Decaluwe
No, it simply means that they prefer that you use their proprietary
language, thereby making it impossible to migrate your design
easily to a competitor.
That makes sense - to Altera.
Jan
--
===================================================================
Jan Decaluwe === Easics ===
Design Manager === VHDL-based ASIC design services ===
Tel: +32-16-395 600 ===================================
Fax: +32-16-395 619 Interleuvenlaan 86, B-3001 Leuven, BELGIUM
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Adge
for Altera devices in AHDL than VHDL.
AHDL can be easier to read too.
Adge
Jan Decaluwe wrote in message <3741219E...@easics.be>...
Peter Sørensen
error free. And you have every thing in
the Altera tool.
VHDL is for large designs and takes some time to learn.
VHDL is a standard and some code can be ported without change.
You need 3 party tools like VHDL simulator and synthesis to get the advances of
VHDL.
But VHDL simulators are much faster and you can write testbenches as code.
Simulation of complex designs are impractical slow and diffecult in AHLD.
Further the Altera VHDL synthesis has errors, see my news subject: Warning:
Altera VHDL synthesis error
Thai Hoa Vo wrote:
> Hi
>
> Altera suggests to use AHDL instead of VHDL. Does it mean that AHDL
> give a better optimization in term of resource and performance ?
>
> Thank you.
Peter Sørensen
exactly the same results in AHLD and VHDL. Altera translate VHDL to binary AHDL
as far as I know. If you use 3 party VHDL synthesis you may bet better or worse
results. AHDL force you to thing in HW, while in VHDL you may use more high
level abstractions then get difference results.
Renaud Pacalet
>
> Hi
>
> Altera suggests to use AHDL instead of VHDL. Does it mean that AHDL
> give a better optimization in term of resource and performance ?
>
> Thank you.
There are a lot of differences between AHDL and VHDL:
- You can't simulate AHDL (MAX+PLUSII simulates the result of
synthesis, not the AHDL you wrote).
- VHDL allows high level description (I mean descriptions you can't
synthesize), AHDL doesn't.
- VHDL is a real functional HDL (you describe the what, not the
how). AHDL is mainly a structural HDL, with a few functional
features.
- With VHDL you can design high level test benches, not in AHDL.
- VHDL is portable, AHDL is not.
But AHDL part of MAX+PLUSII is much less bugged than VHDL part.
--
Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13
Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 | Mel : pac...@enst.fr
jok
very powerful and thus in the hands of a computer scientist could lead to
poor hardware design. I think the AHDL takes advantage of the architecture
of the known target device and thus one will get better optimization and can
get away with some 'less than portable' constructs.
I think it depends on what your goals are. In general, I believe Altera has
top notch tools and most likely will be shaking the silicon tree in the next
few years.
Regards,
Jim
John Janusson
I worked on a large project where we used AHDL as the design language.
After having to switch to VHDL, I agree that in many ways AHDL is
technically a better language... VHDL can be quite retarded (sorry,
mentally challenged). The famous competing "=" signs in std_logic_1164 and
std_logic_unsigned is a good example. Of course with AHDL your stuck using
Altera's software and devices. It's always good to be able to switch
vendors (Altera to Xilinx) and technologies (FPGA to ASIC). It's much
easier to do using VHDL and a 3rd party synthesizer and simulator...
JJ
jok wrote in message <7ikvlv$lmg$1...@autumn.news.rcn.net>...
Jan Decaluwe
>
> VHDL can be quite retarded (sorry,
> mentally challenged). The famous competing "=" signs in std_logic_1164 and
> std_logic_unsigned is a good example.
You shouldn't blame the language and the power it provides
for flagrant misuse, such as the design of a package
like std_logic_unsigned.
Regards, Jan
--
Jan Decaluwe Easics
Design Manager SoC design services & web tools
+32-16-395 600 Interleuvenlaan 86, B-3001 Leuven, Belgium
mailto:ja...@easics.be http://www.easics.com
John Janusson
Whatever... I was just trying to stick up for AHDL as a decent (albeit less
powerful) HDL. Since I make my living (in part) doing VHDL designs, I'm not
going to complain about it too much 8>)
One thing I wish you could do (elegantly) in VHDL is a truth table ala
Verilog or AHDL. Any suggestions??? For example, this is what an AHDL
"and" gate truth table looks:
TABLE
a, b => c
0, 0 => 0
0, 1 => 0
1, 0 => 0
1, 1 => 1
END TABLE;
The closest I can really think of in VHDL is a when-else...
c <= --ab
0 when a_b = "00" else
0 when a_b = "01" else
0 when a_b = "10" else
1 when a_b = "11" else;
JJ
Jan Decaluwe wrote in message <374EBFBC...@easics.be>...
me...@mench.com
> John Janusson wrote:
>> Ok, how bout VHDL using "<=" for both less-than-or-equal and assignment...
>
> except if they have had too much C exposure. VHDL assignments cannot
> occur in expressions.
Actually, it's not even an issue for parsers, for the very same reason.
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OrCAD | www.orcad.com | spread fear, uncertainty and doubt
P.O. Box 71767 | 919-479-1670[v] | in the users' minds."
Durham, NC 27722-1767 | 919-479-1671[f] | --Don Jones, MS's Y2K Product Mgr
James Hurt
>
> Ok, how bout VHDL using "<=" for both less-than-or-equal and assignment...
>
> powerful) HDL. Since I make my living (in part) doing VHDL designs, I'm not
> going to complain about it too much 8>)
>
> One thing I wish you could do (elegantly) in VHDL is a truth table ala
> Verilog or AHDL. Any suggestions??? For example, this is what an AHDL
> "and" gate truth table looks:
>
> TABLE
> a, b => c
> 0, 0 => 0
> 0, 1 => 0
> 1, 0 => 0
> 1, 1 => 1
> END TABLE;
>
> The closest I can really think of in VHDL is a when-else...
>
> c <= --ab
> 0 when a_b = "00" else
> 0 when a_b = "01" else
> 0 when a_b = "10" else
> 1 when a_b = "11" else;
>
> JJ
How about the following:
temp <= a&b;
with temp select
c <= '0' when "00" | "01" | "10",
'1' when "11",
'X' when others;
-- James Y Hurt
Jan Decaluwe
>
> Ok, how bout VHDL using "<=" for both less-than-or-equal and assignment...
That might be an issue for VHDL parsers, but not for designers, except
if they
have had too much C exposure. VHDL assignments cannot occur in
expressions.
> One thing I wish you could do (elegantly) in VHDL is a truth table ala
> Verilog or AHDL. Any suggestions??? For example, this is what an AHDL
> "and" gate truth table looks:
In VHDL, we would use the "and" operator for this :-)
Regards, Jan
Wade D. Peterson
news:7imoaa$32i$1...@eng25.eng.I-O.com...
[snip]
> One thing I wish you could do (elegantly) in VHDL is a truth table ala
> Verilog or AHDL. Any suggestions??? For example, this is what an AHDL
> "and" gate truth table looks:
>
> a, b => c
> 0, 0 => 0
> 0, 1 => 0
> 1, 0 => 0
> 1, 1 => 1
> END TABLE;
I agree. A truth table function would be nice.
We came up with a solution a couple of years ago that works amazingly well. We
wrote a little 'C++' program that reads a truth table from an ASCII file,
generates VHDL code (logic equations), and sends it to an output file. The
final code was complete with entity, port and architecture statements. It
really wasn't very hard to do. The output logic appears as 'case',
'if-then-else' or 'and' type equations. The type of statement was selected with
a software switch.
I would post the 'C++' source code but unfortunately it was done as a customer
special, and they own the IP. As I remember, it only took a couple of days to
do it, though.
--
Wade D. Peterson
Silicore Corporation
3525 E. 27th St. No. 301, Minneapolis, MN USA 55406
TEL: (612) 722-3815, FAX: (612) 722-5841
URL: http://www.silicore.net/ E-MAIL: pete...@maroon.tc.umn.edu
Renaud Pacalet
>
> Ok, how bout VHDL using "<=" for both less-than-or-equal and assignment...
>
> powerful) HDL. Since I make my living (in part) doing VHDL designs, I'm not
> going to complain about it too much 8>)
>
> Verilog or AHDL. Any suggestions??? For example, this is what an AHDL
> "and" gate truth table looks:
>
> TABLE
> a, b => c
> 0, 0 => 0
> 0, 1 => 0
> 1, 0 => 0
> 1, 1 => 1
> END TABLE;
>
>
> c <= --ab
> 0 when a_b = "00" else
> 0 when a_b = "01" else
> 0 when a_b = "10" else
> 1 when a_b = "11" else;
>
> JJ
>
function MY_AND(A, B: BIT) return BIT is
type T is array(BIT range '0' to '1', BIT range '0' to '1') of BIT;
-- 0 1
constant C_AND: T := (('0', '0'), -- 0
('0', '1')); -- 1
begin
return C_AND(A, B);
end MY_AND;