Open Source VHDL Verification Methodology (OSVVM) is VHDL’s leading edge verification methodology. OSVVM makes adding functional coverage, randomization, and Intelligent Coverage (coverage driven randomization) to your VHDL testbench simple, concise, and powerful.
With OSVVM, you don't need a specialized verification language such as SystemVerilog or 'e' to do verification, in fact, in many key areas, OSVVM is a step ahead.