how to shift in VHDL

Jean-Charles FRANCK

unread,

Mar 2, 1999, 3:00:00 AM3/2/99

to

Hello,
I'm a new user of VHDL and I don't manage to shifting a std_logic_vector
.Someone told me that I could use SLL or SRL to shift left or rightit hasn't
worked.Could you HELP me.
Thanks in advance,
Jean-Charles

Lev Razamat

unread,

Mar 2, 1999, 3:00:00 AM3/2/99

to

this is very simple in VHDL

.
.
.
signal shiftreg : std_logic_vector (7 downto 0);
.
.
.
shiftreg(7 downto 1) <= shifreg(6 downto 0);
shiftreg(0) <= any_input__or_internal_signal;

off course every think should be under clock

good luck

Jean-Charles FRANCK <je...@teleriviera.fr> wrote in message
news:7bhfmb$52u$1...@news.entreprises.cegetel.fr...

me...@mench.com

unread,

Mar 2, 1999, 3:00:00 AM3/2/99

to

Lev Razamat <lraz...@netvision.net.il> wrote:
> signal shiftreg : std_logic_vector (7 downto 0);
> .
> .
> .
> shiftreg(7 downto 1) <= shifreg(6 downto 0);
> shiftreg(0) <= any_input__or_internal_signal;

Or, more simply,

shiftreg <= shiftreg(6 downto 0) & fill_bit;

This example does a left shift. All other shifts and rotates are
possible with different combinations of indexing, slicing, and
concatenation.

Paul

Q. Yang

unread,

Mar 3, 1999, 3:00:00 AM3/3/99

to

I think the IEEE std_logic_(unsiged? arith?) has function SHR(std_logic_vector
to be shifted, amount of shifting in std_logic_vector) for shift right and
similar function for shift left. IEEE numeric_std has a slightly different
version.
Both are supported by Synopsys synthesis. The best way to make sure where the
functions are is to look at the
VHDL source of these packages.

Q. Yang

Cameron Watt

unread,

Mar 5, 1999, 3:00:00 AM3/5/99

to

The SRL SLL are VHDL '93, so if you are using VHDL '87 they won't be supported,
best is to use the concatenation and slicing method as mentioned by others.

Cheers,

Cameron Watt

Robert Bell

unread,

Mar 5, 1999, 3:00:00 AM3/5/99

to

Cameron Watt wrote:

> The SRL SLL are VHDL '93, so if you are using VHDL '87 they won't be supported,
> best is to use the concatenation and slicing method as mentioned by others.
>
> Cheers,
>
> Cameron Watt

Is this true? I don't think so since I am using them in code compiled as
'87 code. I also thought that this was independent of the age of a
particular VHDL dialect and instead an issue of the difference
between 1076 and 1164.

rabell ...
Robert Bell

Robert Bell

unread,

Mar 5, 1999, 3:00:00 AM3/5/99

to

Robert Bell wrote:

Sorry, my fault. I was mixing SLL/SRL and SHL/SHR.

I am using SHL/SHR and having no problem with sim or
synth (yet).

rabell ...

me...@mench.com

unread,

Mar 5, 1999, 3:00:00 AM3/5/99

to

Robert Bell <rab...@ti.com> wrote:
> Cameron Watt wrote:
>> The SRL SLL are VHDL '93, so if you are using VHDL '87 they won't be
>> supported, best is to use the concatenation and slicing method as
>> mentioned by others.

> Is this true? I don't think so since I am using them in code

> compiled as '87 code. I also thought that this was independent of
> the age of a particular VHDL dialect and instead an issue of the
> difference between 1076 and 1164.

The shift and rotate operators were added as part of VHDL'93.

Loc Mai

unread,

Mar 9, 1999, 3:00:00 AM3/9/99

to

Hi there,
I did not use either SLL , SRL , SHL ...
I extracted and rewrote a portion of my successful design in CPLD
implementation.
Hope it works for you.
-----------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.std_arith.all;
ENTITY shifting IS PORT ( PORST, clk, shift_en, serialdata:in std_logic;
dffout: out std_logic_vector(11 downto 0));
END shifting;

ARCHITECTURE arcword0det OF shifting IS
SIGNAL registerword :std_logic_vector(11 downto 0):= "000000000000";--initial
signal :std_logic;

BEGIN
s2p:PROCESS(porst, clk, shift_en, registerRST)
variable presentword :std_logic_vector(11 downto 0);-- Declarations
BEGIN
if porst = '0' then --porst is Async clr
presentword := "000000000000";
elsif rising_edge(clk) then
if shift_en = '0' then
presentword(11) := serialdata;
presentword(10 downto 0) := registerword(11 downto 1);
end if;
end if;
registerword <= presentword;--LSB leads in bit stream
dffout <= presentword
END PROCESS s2p;
-------------------
END arcword0det;

--------------------------------------------------------

In article <36DCB65C...@ucsu.colorado.edu>,

"Q. Yang" <ya...@ucsu.colorado.edu> wrote:
> I think the IEEE std_logic_(unsiged? arith?) has function SHR(std_logic_vector
> to be shifted, amount of shifting in std_logic_vector) for shift right and
> similar function for shift left. IEEE numeric_std has a slightly different
> version.
> Both are supported by Synopsys synthesis. The best way to make sure where the
> functions are is to look at the
> VHDL source of these packages.
>
> Q. Yang
>

> Jean-Charles FRANCK wrote:
>
> > Hello,
> > I'm a new user of VHDL and I don't manage to shifting a std_logic_vector
> > .Someone told me that I could use SLL or SRL to shift left or rightit hasn't
> > worked.Could you HELP me.
> > Thanks in advance,
> > Jean-Charles
>
>

DND DREO
(613)998-2092

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own