PORT MAP assignment

[Florian Finsterbusch]

I have created some components with 8-bit input and output registers to
control external devices.
Now i want to assign signals to these 8-bit ports in the instances with the
PORT MAP command.
But not all inputs or outputs of these port will be used.
Is there something like OTHERS => '0' to assign the unused I/Os to a default
state?

Best regards, Florian

[Srinivasan Venkataramanan]

Hi Florian,
You can leave unused outputs as "open" (that's a key-word
introduced 10 years ago! - VHDL'93 :-) ). But inputs must be driven.

HTH,
Srinivasan

--
Srinivasan Venkataramanan
Senior Verification Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

http://www.noveldv.com http://www.deeps.org

I don't speak for Intel
"Florian Finsterbusch" <f.finst...@lightmaze.com> wrote in message
news:1e5adc5c.0305...@posting.google.com...

[Kim Noer]

"Srinivasan Venkataramanan" <srini...@siliconsystems.no_spam.co.in>
wrote in message news:bad3pg$521$1...@news01.intel.com

> Hi Florian,
> You can leave unused outputs as "open" (that's a key-word
> introduced 10 years ago! - VHDL'93 :-) ). But inputs must be driven.

I usually bind them to a signal, which makes it easier for me to track what
I don't use. But it of course requires more typing.

--
I doubt, therefore I might be.

[Egbert Molenkamp]

"Srinivasan Venkataramanan" <srini...@siliconsystems.no_spam.co.in> wrote
in message news:bad3pg$521$1...@news01.intel.com...

> Hi Florian,
> You can leave unused outputs as "open" (that's a key-word
> introduced 10 years ago! - VHDL'93 :-) ). But inputs must be driven.
>

But if the input has an explicit value in de component declaration also OPEN
can be used for inputs.
E.g. in the following code the synthesis tool we use connects the reset
input of INST with GND.
and if
reset : in std_logic := '0';
is changed in:
reset : in std_logic := '1';
The tool connect the q output with GND.

I'm not sure if all synthesis tool can handle this.

Egbert Molenkamp

library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (d : in std_logic;
q : out std_logic;
reset : in std_logic := '0';
clk : in std_logic);
end entity dff;

architecture behaviour of dff is
begin
process (reset,clk)
begin
if reset='1' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process;
end behaviour;

library ieee;
use ieee.std_logic_1164.all;
entity inst is
port (d : in std_logic;
q : out std_logic;
clk : in std_logic);
end entity inst;

architecture struct of inst is
component dff is
port (d : in std_logic;
q : out std_logic;
reset : in std_logic := '0';
clk : in std_logic);
end component dff;
begin
i : dff port map (d,q,OPEN,clk);
end struct;

[Florian Finsterbusch]

Thank you all for your comments!

My I/O registers components have 8-bit wide inputs and outputs:
PORT (
...
OREG_DATA : out std_logic_vector (7 downto 0));

For one instance i've used the following assignment (only 1 output is used
at the moment):

PORT MAP (
...
OREG_DATA(0) => PC_ERRn);

This works fine when using Quartus-II.
But now i also want to simulate with Modelsim and get the following error:
"Aggregate length is 1. Expected length is 8."
How could i get rid of this error?
How must i assign OREG_DATA(7 downto 1)?

Is there a convenient way to assign unused signals:

OREG_DATA => (0 => PC_ERRn, others => open)
Outputs one signal. The six unused bits of the register should not be used

IREG_DATA => (0 => PWR_OK, 1 => RESn, others => '0')
Inputs two signals. The six unused bits of the register should be read as
'0'

Is something like this possible or must i assign every unused signal
separately?

Best regards, Florian

"Kim Noer" <k...@nospam.dk> schrieb im Newsbeitrag
news:bad525$s1pro$1...@ID-151686.news.dfncis.de...

> "Srinivasan Venkataramanan" <srini...@siliconsystems.no_spam.co.in>
> wrote in message news:bad3pg$521$1...@news01.intel.com
>

> > Hi Florian,
> > You can leave unused outputs as "open" (that's a key-word
> > introduced 10 years ago! - VHDL'93 :-) ). But inputs must be driven.
>

[Srinivasan Venkataramanan]

Hi Florian,
VHDL 87 used to allow this "partial assignment to OPEN" (in a
vector or a composite type), but this was considered a "bug" and hence
was dis allowed in 1993 LRM. I know that NCSIm still allows it, but
modelsim doesn't.

So your solution would be to use a dummy signal.

HTH,
Srinivasan
http://www.noveldv.com

f.finst...@lightmaze.com (Florian Finsterbusch) wrote in message news:<1e5adc5c.03052...@posting.google.com>...