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Unconstrained Array of Unconstrained Array
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Weng Tianxiang
Sep 17, 2014, 8:13:41 PM9/17/14
to
Hi,
This is a 16 years old problem.
I want to know if VHDL-2008 resolved the problem or not. Why?
Thank you.
Weng
Unconstrained Array of Unconstrained Array
5 posts by 4 authors
Jose Paredes
2/12/98
Is it possible to define an unconstrained array of unconstrained arrays?
Something like this:
type array_type is array(natural range <>) of std_logic_vector;
I find myself needing something like this where it would be used in an
entity definition like this:
entity ...
port( a : in array_type(0 to width1-1)(0 to width2-1) ...
...
Of course, I know that the above is wrong syntax, but is there something
equivalent other than a double dimensional unconstrained array?
Ultimately what I want is for the entity to be used like this:
signal bus1 : std_logic_vector(0 to 31);
signal bus2 : std_logic_vector(0 to 31);
...
-- instantiate entity
ENTITY1 : ENTITY_NAME
generic map( width1 => 2, width2 => 32);
port map(a(0) => bus1,
a(1) => bus2);
This essentially creates 2 ports called a(0) and a(1) into my entity
that are 32 bits wide. Surely something very close to this has been done
before.
Thanks for any help,
Jose
--
Jose A. Paredes
IBM
11400 Burnet Road
Internal Mail 4362
Austin, TX 78758
office: 512-838-3855
fax: 512-838-1258
email: jo...@austin.ibm.com
Click here to Reply
Pam Rissmann
2/12/98
Jose,
Unfortunately, VHDL doesn't allow an unconstrained array
of an unconstrained array. The element type and size (what the array
holds) must be a known quantity.
>type array_type is array(natural range <>) of std_logic_vector;
^^^^^^^^^^^^^^^^^
element type
However, you can have
an unconstrained array of a std_logic_vector(31 downto 0).
And like you said, a unconstrained 2 dimensional array of
std_logic is allowed.
For your application, maybe you can workaround this
by creating a package that defines a constrained subtype
of std_logic_vector by using a constant set to the same
value as your width2 generic.
something like:
constant c_width2: integer := 32; -- can also make this deferred
subtype stdv32 is std_logic_vector(c_width2-1 downto 0);
type array_type is array(natural range <>) of stdv32;
Hope this helps.
--Pam
_______________________________________________
Pam Rissmann - Magenta Designs - 650.325.1162
- show quoted text -
-
Dave Jacobowitz
2/16/98
Pam Rissmann wrote:
>
> Jose,
> Unfortunately, VHDL doesn't allow an unconstrained array
> of an unconstrained array. The element type and size (what the array
> holds) must be a known quantity.
Not to belabor this point, but I have a similar question. I want
to do something that I thought would be pretty easy: create a
memory that would take generics to set the depth and width and
number each of read, write, and cam ports. I tried something like
what I have included below. Here none of the arrays are unconstrained,
their sizes are all set by the generics given. My problem is that
the the VHDL syntax does not seem to support the definition of
arrays within the port section.
Creating subtypes ahead of time in a package solves this problem,
but only partially, since if I want to include multiple instances
of this entity with varying sizes and ports, I'll have to make
multiple copies of the source and actually change them, defeating
the purpose of the generics altogether.
Can VHDL really not do this?
-- dave jacobowitz (dja...@quickturn.com)
------------------------------------------------------------
entity hcam is
generic ( width : integer := 32;
addrwidth : integer := 5;
depth : integer := 32;
rports : integer := 1;
wports : integer := 1;
kports : integer := 1);
port ( clock : std_logic;
read_address_in : in array (rports-1 downto 0) of unsigned
(addrwidth-1 downto 0);
read_data_out : out array (rports-1 downto 0) of
std_logic_vector (width-1 downto 0);
read_en : in std_logic_vector(rports-1 downto 0);
write_address_in : in array (wports-1 downto 0) of unsigned
(addrwidth-1 downto 0);
write_data_in : in array (wports-1 downto 0) of
std_logic_vector (width-1 downto 0);
write_en : in std_logic_vector(wports-1 downto 0);
key_data_in : in array (kports-1 downto 0) of
std_logic_vector (width-1 downto 0);
key_match : out std_logic_vector(kports-1 downto 0);
key_matchaddr : out array (kports-1 downto 0) of unsigned
(addrwidth-1 downto 0);
key_cam_en : in std_logic_vector(kports-1 downto 0);
end hcam;
Martin Radetzki
2/17/98
Dave Jacobowitz wrote:
>
> Pam Rissmann wrote:
> >
> > Jose,
> > Unfortunately, VHDL doesn't allow an unconstrained array
> > of an unconstrained array. The element type and size (what the array
> > holds) must be a known quantity.
>
> Not to belabor this point, but I have a similar question. I want
> to do something that I thought would be pretty easy: create a
> memory that would take generics to set the depth and width and
> number each of read, write, and cam ports. I tried something like
> what I have included below. Here none of the arrays are unconstrained,
> their sizes are all set by the generics given. My problem is that
> the the VHDL syntax does not seem to support the definition of
> arrays within the port section.
>
> Creating subtypes ahead of time in a package solves this problem,
> but only partially, since if I want to include multiple instances
> of this entity with varying sizes and ports, I'll have to make
> multiple copies of the source and actually change them, defeating
> the purpose of the generics altogether.
>
> Can VHDL really not do this?
>
> -- dave jacobowitz (dja...@quickturn.com)
>
Well, VHDL can do it using a 2-dimensional array
declared in some package:
type STD_LOGIC_ARRAY is
array( NATURAL range <>, NATURAL range <> )
of STD_LOGIC;
Then, declare the ports like this:
read_address_in : in STD_LOGIC_ARRAY( rports-1 downto 0,
addrwidth-1 downto 0 );
...
Using this approach, one can't use type UNSIGNED for the port,
but conversion should be possible, the elements (single bits)
of the UNSIGNED vector and the STD_LOGIC_ARRAY are compatible
for assignment. However, due to type mismatch, it will not be
possible to assign a complete UNSIGNED vector to a row of the
2-dim array, unfortunately.
Thus, unless someone else has another solution, the approach
to declare the width of ports as constants in a package
may be easier to deal with than this 2-dim array approach.
- show quoted text -
________________________________________________________________________
Martin Radetzki Tel.: **49-441-798-2988
OFFIS Research Institute Fax.: **49-441-798-2145
Escherweg 2 http://eis.informatik.uni-oldenburg.de/~martin
26121 Oldenburg, Germany e-mail: rade...@offis.uni-oldenburg.de
Jose Paredes
2/20/98
Dave,
I was trying to do the same thing as you. The only solution is to have a
2-dimensional array. This makes the code a little unreadable, because
when you actually use the outputs of the RAM you can't just assign a one
of the outputs to a logic vector signal, like you would have been able
to if you had an array of arrays. For instance:
-- somwhere in a package :
-- two ram output ports of width 8
TYPE array_type1 is array (0 to 1) of std_logic_vector(0 to 7);
-- entity
ENTITY ram is (
...
outputports : out array_type1
...
-- somewhere else you would want
signal ram_port0(0 to 7);
signal ram_port1(0 to 7);
RAM0 : ram
port map(
...
outputports(0) => ram_port0,
outputports(1) => ram_port1,
...
This is all valid syntax. The problem is that since the second the
std_logic_vector(0 to 7) must be there, you can't make the width of the
port generic. So you have to implement something nasty:
-- somwhere in a package :
--
TYPE array_type2 is array (integer range <>, integer range <>) of
std_logic;
-- entity
ENTITY ram is (
...
outputports : out array_type2(0 to 1, 0 to 7)
...
-- somewhere else you would want
signal ram_port0(0 to 7);
signal ram_port1(0 to 7);
RAM0 : ram
port map(
...
outputports(0,0) => ram_port0(0),
outputports(0,1) => ram_port0(1),
outputports(0,2) => ram_port0(2),
...
outputports(1,0) => ram_port1(0),
outputports(1,1) => ram_port1(1),
outputports(1,2) => ram_port1(2),
..
Which is simply ridiculous. I find the language inconsistent in this
matter, because there is no reason, in my opinion, why you could not
have been able to resolve both constraints of an array of arrays:
-- package
type array_type is array(integer range <>) of std_logic_vector;
-- somewhere else
entity ram is
port(
...
-- why is this not allowed?
multi_port : array_type(0 to 1)(0 to 7);
I don't understand exactly why this is not allowed, since there is
really nothing magical about this (other than not being correct
syntax...). I assume it has something to do with strong typing in VHDL
which I also believe that in some cases it hinders productivity (like in
this case). Just my 2 centavos...
Jose
--
Jose A. Paredes
IBM
11400 Burnet Road
Internal Mail 4362
Austin, TX 78758
office: 512-838-3855
fax: 512-838-1258
email: jo...@austin.ibm.com
This is a 16 years old problem.
I want to know if VHDL-2008 resolved the problem or not. Why?
Thank you.
Weng
Unconstrained Array of Unconstrained Array
5 posts by 4 authors
Jose Paredes
2/12/98
Is it possible to define an unconstrained array of unconstrained arrays?
Something like this:
type array_type is array(natural range <>) of std_logic_vector;
I find myself needing something like this where it would be used in an
entity definition like this:
entity ...
port( a : in array_type(0 to width1-1)(0 to width2-1) ...
...
Of course, I know that the above is wrong syntax, but is there something
equivalent other than a double dimensional unconstrained array?
Ultimately what I want is for the entity to be used like this:
signal bus1 : std_logic_vector(0 to 31);
signal bus2 : std_logic_vector(0 to 31);
...
-- instantiate entity
ENTITY1 : ENTITY_NAME
generic map( width1 => 2, width2 => 32);
port map(a(0) => bus1,
a(1) => bus2);
This essentially creates 2 ports called a(0) and a(1) into my entity
that are 32 bits wide. Surely something very close to this has been done
before.
Thanks for any help,
Jose
--
Jose A. Paredes
IBM
11400 Burnet Road
Internal Mail 4362
Austin, TX 78758
office: 512-838-3855
fax: 512-838-1258
email: jo...@austin.ibm.com
Click here to Reply
Pam Rissmann
2/12/98
Jose,
Unfortunately, VHDL doesn't allow an unconstrained array
of an unconstrained array. The element type and size (what the array
holds) must be a known quantity.
>type array_type is array(natural range <>) of std_logic_vector;
^^^^^^^^^^^^^^^^^
element type
However, you can have
an unconstrained array of a std_logic_vector(31 downto 0).
And like you said, a unconstrained 2 dimensional array of
std_logic is allowed.
For your application, maybe you can workaround this
by creating a package that defines a constrained subtype
of std_logic_vector by using a constant set to the same
value as your width2 generic.
something like:
constant c_width2: integer := 32; -- can also make this deferred
subtype stdv32 is std_logic_vector(c_width2-1 downto 0);
type array_type is array(natural range <>) of stdv32;
Hope this helps.
--Pam
_______________________________________________
Pam Rissmann - Magenta Designs - 650.325.1162
- show quoted text -
-
Dave Jacobowitz
2/16/98
Pam Rissmann wrote:
>
> Jose,
> Unfortunately, VHDL doesn't allow an unconstrained array
> of an unconstrained array. The element type and size (what the array
> holds) must be a known quantity.
Not to belabor this point, but I have a similar question. I want
to do something that I thought would be pretty easy: create a
memory that would take generics to set the depth and width and
number each of read, write, and cam ports. I tried something like
what I have included below. Here none of the arrays are unconstrained,
their sizes are all set by the generics given. My problem is that
the the VHDL syntax does not seem to support the definition of
arrays within the port section.
Creating subtypes ahead of time in a package solves this problem,
but only partially, since if I want to include multiple instances
of this entity with varying sizes and ports, I'll have to make
multiple copies of the source and actually change them, defeating
the purpose of the generics altogether.
Can VHDL really not do this?
-- dave jacobowitz (dja...@quickturn.com)
------------------------------------------------------------
entity hcam is
generic ( width : integer := 32;
addrwidth : integer := 5;
depth : integer := 32;
rports : integer := 1;
wports : integer := 1;
kports : integer := 1);
port ( clock : std_logic;
read_address_in : in array (rports-1 downto 0) of unsigned
(addrwidth-1 downto 0);
read_data_out : out array (rports-1 downto 0) of
std_logic_vector (width-1 downto 0);
read_en : in std_logic_vector(rports-1 downto 0);
write_address_in : in array (wports-1 downto 0) of unsigned
(addrwidth-1 downto 0);
write_data_in : in array (wports-1 downto 0) of
std_logic_vector (width-1 downto 0);
write_en : in std_logic_vector(wports-1 downto 0);
key_data_in : in array (kports-1 downto 0) of
std_logic_vector (width-1 downto 0);
key_match : out std_logic_vector(kports-1 downto 0);
key_matchaddr : out array (kports-1 downto 0) of unsigned
(addrwidth-1 downto 0);
key_cam_en : in std_logic_vector(kports-1 downto 0);
end hcam;
Martin Radetzki
2/17/98
Dave Jacobowitz wrote:
>
> Pam Rissmann wrote:
> >
> > Jose,
> > Unfortunately, VHDL doesn't allow an unconstrained array
> > of an unconstrained array. The element type and size (what the array
> > holds) must be a known quantity.
>
> Not to belabor this point, but I have a similar question. I want
> to do something that I thought would be pretty easy: create a
> memory that would take generics to set the depth and width and
> number each of read, write, and cam ports. I tried something like
> what I have included below. Here none of the arrays are unconstrained,
> their sizes are all set by the generics given. My problem is that
> the the VHDL syntax does not seem to support the definition of
> arrays within the port section.
>
> Creating subtypes ahead of time in a package solves this problem,
> but only partially, since if I want to include multiple instances
> of this entity with varying sizes and ports, I'll have to make
> multiple copies of the source and actually change them, defeating
> the purpose of the generics altogether.
>
> Can VHDL really not do this?
>
> -- dave jacobowitz (dja...@quickturn.com)
>
Well, VHDL can do it using a 2-dimensional array
declared in some package:
type STD_LOGIC_ARRAY is
array( NATURAL range <>, NATURAL range <> )
of STD_LOGIC;
Then, declare the ports like this:
read_address_in : in STD_LOGIC_ARRAY( rports-1 downto 0,
addrwidth-1 downto 0 );
...
Using this approach, one can't use type UNSIGNED for the port,
but conversion should be possible, the elements (single bits)
of the UNSIGNED vector and the STD_LOGIC_ARRAY are compatible
for assignment. However, due to type mismatch, it will not be
possible to assign a complete UNSIGNED vector to a row of the
2-dim array, unfortunately.
Thus, unless someone else has another solution, the approach
to declare the width of ports as constants in a package
may be easier to deal with than this 2-dim array approach.
- show quoted text -
________________________________________________________________________
Martin Radetzki Tel.: **49-441-798-2988
OFFIS Research Institute Fax.: **49-441-798-2145
Escherweg 2 http://eis.informatik.uni-oldenburg.de/~martin
26121 Oldenburg, Germany e-mail: rade...@offis.uni-oldenburg.de
Jose Paredes
2/20/98
Dave,
I was trying to do the same thing as you. The only solution is to have a
2-dimensional array. This makes the code a little unreadable, because
when you actually use the outputs of the RAM you can't just assign a one
of the outputs to a logic vector signal, like you would have been able
to if you had an array of arrays. For instance:
-- somwhere in a package :
-- two ram output ports of width 8
TYPE array_type1 is array (0 to 1) of std_logic_vector(0 to 7);
-- entity
ENTITY ram is (
...
outputports : out array_type1
...
-- somewhere else you would want
signal ram_port0(0 to 7);
signal ram_port1(0 to 7);
RAM0 : ram
port map(
...
outputports(0) => ram_port0,
outputports(1) => ram_port1,
...
This is all valid syntax. The problem is that since the second the
std_logic_vector(0 to 7) must be there, you can't make the width of the
port generic. So you have to implement something nasty:
-- somwhere in a package :
--
TYPE array_type2 is array (integer range <>, integer range <>) of
std_logic;
-- entity
ENTITY ram is (
...
outputports : out array_type2(0 to 1, 0 to 7)
...
-- somewhere else you would want
signal ram_port0(0 to 7);
signal ram_port1(0 to 7);
RAM0 : ram
port map(
...
outputports(0,0) => ram_port0(0),
outputports(0,1) => ram_port0(1),
outputports(0,2) => ram_port0(2),
...
outputports(1,0) => ram_port1(0),
outputports(1,1) => ram_port1(1),
outputports(1,2) => ram_port1(2),
..
Which is simply ridiculous. I find the language inconsistent in this
matter, because there is no reason, in my opinion, why you could not
have been able to resolve both constraints of an array of arrays:
-- package
type array_type is array(integer range <>) of std_logic_vector;
-- somewhere else
entity ram is
port(
...
-- why is this not allowed?
multi_port : array_type(0 to 1)(0 to 7);
I don't understand exactly why this is not allowed, since there is
really nothing magical about this (other than not being correct
syntax...). I assume it has something to do with strong typing in VHDL
which I also believe that in some cases it hinders productivity (like in
this case). Just my 2 centavos...
Jose
--
Jose A. Paredes
IBM
11400 Burnet Road
Internal Mail 4362
Austin, TX 78758
office: 512-838-3855
fax: 512-838-1258
email: jo...@austin.ibm.com
Daniel Kho
Sep 17, 2014, 11:40:47 PM9/17/14
to
I have used the following for as long as I can remember. Synthesis support was available only as far back as 2007/2008 or so, but I believe there is nothing in the language that prevents us from writing this.
type memory_vector is array(0 to memoryWidth-1) of unsigned(din'range);
type memory_matrix is array(0 to memoryDepth-1) of memory_vector;
signal ram_matrix: memory_matrix:=(others=>(others=>(others=>'0')));
-- within the architecture body:
ram_matrix(writeAddr_h)(writeAddr_v)<=din;
Of course, it's always better to use multi-dimensional arrays if you can. Synthesis support for this is poor though.
type memory_matrix2d is array(0 to memoryWidth-1, 0 to memoryDepth-1) of unsigned(din'range);
signal ram_matrix2d: memory_matrix2d;
-- within the architecture body:
ram_matrix2d(writeAddr_h,writeAddr_v)<=din;
regards, daniel
rickman
Sep 18, 2014, 12:17:05 AM9/18/14
to
integers for memory. The range of the integer within the module can be
constrained to establish the memory word width. The conversion to what
ever bus type outside the module is simple. Why not make your memory
module an integer based interface and pass in a generic to set the range
of the type for the memory itself. The integers used for wires in and
out don't really care about the range, it won't affect the synthesis.
--
Rick
Daniel Kho
Sep 18, 2014, 12:24:07 AM9/18/14
to
Hi Tianxiang,
I noticed I haven't _really_ answered your question. The short answer is you can't (?) have an unconstrained array of another unconstrained array. Somehow you need to constrain the size of the sub-array, and then you can have the encapsulating array be unconstrained.
But, like what was mentioned in your post, a 2-D array would do what you need. So, this won't work:
type array_type is array(natural range <>, natural range <>) of std_logic;
Synthesis tools still don't efficiently infer memory blocks though.
-daniel
I noticed I haven't _really_ answered your question. The short answer is you can't (?) have an unconstrained array of another unconstrained array. Somehow you need to constrain the size of the sub-array, and then you can have the encapsulating array be unconstrained.
But, like what was mentioned in your post, a 2-D array would do what you need. So, this won't work:
type array_type is array(natural range <>) of std_logic_vector;
But something like this would:
type array_type is array(natural range <>, natural range <>) of std_logic;
Synthesis tools still don't efficiently infer memory blocks though.
-daniel
KJ
Sep 18, 2014, 7:01:10 AM9/18/14
to
On Wednesday, September 17, 2014 8:13:41 PM UTC-4, Weng Tianxiang wrote:
> Hi,
>
> This is a 16 years old problem.
>
> I want to know if VHDL-2008 resolved the problem or not. Why?
>
If you compile with 2008 then yes you can have an unconstrained array of an unconstrained array.
> Hi,
>
> This is a 16 years old problem.
>
> I want to know if VHDL-2008 resolved the problem or not. Why?
>
Kevin Jennings
Weng Tianxiang
Sep 18, 2014, 12:25:25 PM9/18/14
to
Weng
Weng Tianxiang
Sep 18, 2014, 3:03:49 PM9/18/14
to
Thank you very much for your replies.
Weng
rickman
Sep 18, 2014, 5:55:06 PM9/18/14
to
>> Rick
>
> My applications of an unconstrained array of another unconstrained array will be used for everyone in any situations.
If you use integers instead of std_logic_vector or unsigned then you
>
> My applications of an unconstrained array of another unconstrained array will be used for everyone in any situations.
don't really need double arrays, now do you? I think memory can then be
modeled by a single array.
BTW, you really should learn to trim your posts and/or stop using Google
groups for a newsreader. Thunderbird is a good newsreader and
eternal-september.org gives free access to text only newsgroups. All
the double spacing of quotes in Google groups is very obnoxious.
--
Rick
Weng Tianxiang
Sep 19, 2014, 11:52:32 AM9/19/14
to
Rickman,
I am inventing something brand new for HDL and hope to finish it within two or three months. When published, your critical comments are welcome. It has nothing to do with any type of RAM memory.
I really need double arrays, but I found that I don't have to use double unconstrained arrays and found a way to avoid it.
OK! I will pay attention to trimming my posts now, deleting all repeated texts.
Thank you.
Weng
I am inventing something brand new for HDL and hope to finish it within two or three months. When published, your critical comments are welcome. It has nothing to do with any type of RAM memory.
I really need double arrays, but I found that I don't have to use double unconstrained arrays and found a way to avoid it.
OK! I will pay attention to trimming my posts now, deleting all repeated texts.
Thank you.
Weng
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