VHDL Assignment of INOUT signals

[T Y Chan]

Is there a way of giving a signal the characteristic of an "INOUT" signal?
I.E. when either one of them changes, the other follows, a lot like the INOUT
reference of a component signal attribute.

--------------------------- VHDL PROGRAM --------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY tstbnh IS
-- empty entity as test bench
END tstbnh;

ARCHITECTURE bhv OF tstbnh IS

SIGNAL a : std_logic; -- Signal A
SIGNAL b : std_logic; -- Signal b follows c
SIGNAL c : std_logic; -- output c
SIGNAL aoe : std_logic; -- output enable of a
SIGNAL bo : std_logic; -- signal assignment

SIGNAL ztmp : std_logic;

COMPONENT aio
PORT (
a : IN std_logic;
aoe : IN std_logic;
c : INOUT std_logic;
d : OUT std_logic
);
END COMPONENT;

BEGIN

Uout : aio PORT MAP ( a, aoe, c,b);
boe <= c;

END PROCESS;

------------------------------------------------------------------------

When I simulate the above, signal "boe" changes when "c" changes, as
expect. Is there a VHDL construct or syntax such that if "boe" changes,
"c" also changes?

I know this might cause signal contention and other issues, I have a
situation in which I want to change the signal names from one block to
another without having to change every occurance of the orginal name and
bus members.

T. Y. Chan

[Bert Molenkamp]

tyc...@wotangate.sc.ti.com (T Y Chan) writes:
>
> Is there a way of giving a signal the characteristic of an "INOUT" signal?
> I.E. when either one of them changes, the other follows, a lot like the INOUT
> reference of a component signal attribute.
>
> --------------------------- VHDL PROGRAM --------------------------------
> LIBRARY IEEE;
> USE IEEE.std_logic_1164.ALL;
>
> ENTITY tstbnh IS
> -- empty entity as test bench
> END tstbnh;
>
> ARCHITECTURE bhv OF tstbnh IS
>
> SIGNAL a : std_logic; -- Signal A
> SIGNAL b : std_logic; -- Signal b follows c
> SIGNAL c : std_logic; -- output c

> SIGNAL boe : std_logic; -- output enable of a

*********************
Why not an ALIAS used?
ALIAS boe : std_logic IS c;

> SIGNAL bo : std_logic; -- signal assignment
>
> SIGNAL ztmp : std_logic;
>
> COMPONENT aio
> PORT (
> a : IN std_logic;
> aoe : IN std_logic;
> c : INOUT std_logic;
> d : OUT std_logic
> );
> END COMPONENT;
>
> BEGIN
>
> Uout : aio PORT MAP ( a, aoe, c,b);
> boe <= c;
>
> END PROCESS;
>
> ------------------------------------------------------------------------
>
> When I simulate the above, signal "boe" changes when "c" changes, as
> expect. Is there a VHDL construct or syntax such that if "boe" changes,
> "c" also changes?
>
> I know this might cause signal contention and other issues, I have a
> situation in which I want to change the signal names from one block to
> another without having to change every occurance of the orginal name and
> bus members.
>
> T. Y. Chan
>
>

-----------------------------
Egbert Molenkamp
Dept. of Computer Science
University of Twente
PO Box 217
7500 AE Enschede
the Netherlands
email: mole...@cs.utwente.nl