Xilinx: IP Capture/CoreGenerator
Mike Hubert
I am looking into the idea of code reuse with Xilinx Foundation software
(version 4.1i/service pack 3, most recent IP updates: 4x_ip_update1.zip,
eip1_tp1.zip) and I'm having difficulties.
I figured it would be a good idea to start off with creating a simple core,
such as a multiplexer. So I create an HDL-flow project, type in my
multiplexer code, and implement the project.
Next step is to create the core. From within CoreGenerator, IP Capture is
launched. Various files are required, the most important being the .edn
edif netlist. In my multiplexer project directory, I have a .edn netlist
file named time_sim.edn: it must be renamed to <name of multiplexer
module>.edn. So I supply the .edn netlist file, the .vhd source file, the
port mapping is entered, etc etc... IP Capture creates a zip file for the
core, which is to be extracted to the Xilinx directory. Please note that I
have inspected the contents of this .edn file and it seems appropriate -
I'm specifying this because the file's original name, time_sim, seems
totally inappropriate.
So far so good. I create a new project, in which I launch CoreGenerator: my
newly created core is exactly where it should be. I can successfully
generate it. In my project, I open a new schematic page, and in the parts
list my generated multiplexer is there. I instantiate it, add hierarchy
connectors, add the sheet to the project, make it the top-level file, and
click the 'implement' button. This is where things get ugly:
----------
Annotating constraints to design from file "lasttry.ucf" ...
Checking timing specifications ...
Checking expanded design ...
ERROR:NgdBuild:455 - logical net 'DA<0>' has multiple drivers
WARNING:NgdBuild:463 - input pad net 'DA<0>' has an illegal input buffer
ERROR:NgdBuild:466 - input pad net 'DA<0>' has illegal connection
ERROR:NgdBuild:455 - logical net 'DA<1>' has multiple drivers
WARNING:NgdBuild:463 - input pad net 'DA<1>' has an illegal input buffer
ERROR:NgdBuild:466 - input pad net 'DA<1>' has illegal connection
ERROR:NgdBuild:455 - logical net 'DB<0>' has multiple drivers
WARNING:NgdBuild:463 - input pad net 'DB<0>' has an illegal input buffer
ERROR:NgdBuild:466 - input pad net 'DB<0>' has illegal connection
ERROR:NgdBuild:455 - logical net 'DB<1>' has multiple drivers
WARNING:NgdBuild:463 - input pad net 'DB<1>' has an illegal input buffer
ERROR:NgdBuild:466 - input pad net 'DB<1>' has illegal connection
ERROR:NgdBuild:455 - logical net 'N_SEL' has multiple drivers
WARNING:NgdBuild:463 - input pad net 'N_SEL' has an illegal input buffer
ERROR:NgdBuild:466 - input pad net 'N_SEL' has illegal connection
ERROR:NgdBuild:467 - output pad net 'O<0>' has an illegal buffer
ERROR:NgdBuild:467 - output pad net 'O<1>' has an illegal buffer
WARNING:NgdBuild:483 - Attribute "INIT" on "U1/GTS" is on the wrong type of
object. Please see the Constraints Guide for more information on this
attribute.
WARNING:NgdBuild:452 - logical net 'U1/GTS' has no driver
NGDBUILD Design Results Summary:
Number of errors: 12
Number of warnings: 7
---------
The 'implement' step always produces these errors. I am however able to
simulate the core.
I seem to have narrowed the problem down to the .edn netlist file I supply
when creating the core. I got to this conclusion as follows. Within
CoreGenerator, there is a multiplexer exactly similar to mine (same # of
ports of same bit-width) which ships with CoreGenerator. I take the .edn
netlist file supplied with this core, edit it by renaming the ports to
match *my* multiplexer and use this modified .edn file to create my
multiplexer core. Then I have no problems!
I've spent a large amount of time trying different things but to no
avail... By poking around I was able to create some slightly different .edn
files, but none of them work either.
How do you generate an edif netlist file appropriate for use with IP
Capture???
Any help would be greatly appreciated,
Mike Hubert
xiphos.ca