n-bit generic magnitude comparator

[Jan Van Houdt]

Heyz,

I got the following assignment for a Digital Systems class in school: design
in a generic way a n-bit magnitude comparator starting from a 1-bit
magnitude comparator... This is my solution:

-- 1bit magnitude comparator

library ieee;
use ieee.std_logic_1164.all;

ENTITY comp1bit IS
PORT(A,B: IN STD_LOGIC; H,L,X: OUT STD_LOGIC);
END comp1bit;

ARCHITECTURE comp1bit_arch OF comp IS
BEGIN
H <= A AND NOT(B);
L <= NOT(A) AND B;
X <= A AND B;
END comp1bit_arch;

-- end 1bit magnitude comparator

-- generic magnitude comparator

library ieee;
use ieee.std_logic_1164.all;

ENTITY comparator IS
GENERIC(n:
-- n = number of bits to compare
PORT(A, B: STD_LOGIC_VECTOR(n-1 downto 0); G, S, E: STD_LOGIC);
END comparator;

ARCHITECTURE comparator_arch IS

-- SIGNAL H, L, X, EN, OFG, OFK: STD_LOGIC_VECTOR(n-1 DOWNTO 0);

COMPONENT comp1bit PORT(A,B: IN STD_LOGIC; H,L,X: OUT STD_LOGIC);
END COMPONENT;

BEGIN:
-- generate n 1-bit comparators
g1: FOR i IN n-1 DOWNTO 0 GENERATE
U1: comp1bit PORT MAP(A(i), B(i), H(I), L(I), X(I));
END GENERATE;

-- calculate E-output
a1: EN(0) <= X(0);
g1: FOR i IN 1 TO n-1 LOOP
EN(i) <= EN(i-1) AND
-- EN(i) is now the 'AND' of Xi till X0
end loop;
E <= EN(n-1);

-- calculate G-output
O1: OFG(0) <= G(0);
g2: for i in 1 to n-1 loop
OFG(i) <= (EN(i-1) AND H(i)) OR
-- EN(i-1) is the 'AND' of all X's from previous 1-bitcomps
end loop;
G <= OFG(n-1);

-- calculate S-output
o2: OFK(0) <= G(0);
g2: for i in 1 to n-1 loop
OFK(i) <= (EN(i-1) AND L(i)) OR OFK(i-1);
end loop;
S <= OFK(n-1);
END comparator_arch;

Thx alot for any answers ;)

greetz,

JanVH

[Jan Van Houdt]

"Jan Van Houdt" <janva...@yahoo.com> schreef in bericht
news:zPkIb.105635$CD2.4...@phobos.telenet-ops.be...

Nobody.. ?

[Mike Treseler]

Jan Van Houdt wrote:

> Nobody.. ?

Just you.
Consider running a sim on your code to see if it works.

-- Mike Treseler