The best timing diagram editor/simulator?
Lindo St Angel
I'm interested in finding out the relative merits of timing diagram
editor tools like WaveformerPro from SynaptiCAD and TimingDesigner from
Chronology. We need a tool to analyze and document timing between blocks
at the system and unit levels. It would be nice if the tools can
generate stimulus files in VHDL and/or Verilog for use in a testbench.
It seems to me that WaveformerPro and TimingDesigner have about have
about the same level of functionality, but the former is about half the
price. Has anyone looked at both of them? Which one is the better value?
Are there any other vendors I should be looking at?
Thanks in advance.
--
Lindo St. Angel
PrairieComm, Inc.
(847) 797-4085
Konrad Feyerabend
>Thanks in advance.
Hi Lindo,
I've played a bit with Chronology's TimingDesigner and Quickbench.
In my opinion Quickbench is not what you are looking for
when generating Test benches from your timing diagrams since there is
lots of postprocessing required and things are not very well integrated.
Simulation is performed with your standard simuator without any
integration of the timing specification. The results are purely textual.
(for all I know)
Timing Designer looks quite nice, you may add guards that help
you finding inconsistencies in your timing requirements.
E.G. You may specify that b should happen within 2ns after a and
that c should happen within 10 to 20ns after b and then add a probe
that checks whether a and c have minimal distance 25 ns. TimingDesigner
will detect that this requirement is violated and highlight it.
Oddly, you may specify that c should happen no earlier that 25 ns after a,
and TimingDesigner does not complain on this impossible set of constraints.
I can't say much on alternatives: I do not know anything on
WavformerPro since I haven't tested it (yet).
There is a tool called BestBench by Diagonal Systems Inc (www.diagonal.com)
which looks
quite nice for creating testbenches since it seems to be nicely integrated
into simulation andallows you to add arbitrary VHDL/verilog-code to
signal changes. They even support static coverage analysis for the
testing you may perform with the testbench you created. Disclaimer:
I only got a brief introduction to BestBench at EuroVHDL 96 but
did never use it by myself so far and
salespersons tend to exaggerate SOMEtimes on the capabilities of
the tools they try to sell. Unfortunately they do not
provide evaluation copies (at least in Europe).
I'm not sure on the documentation facilities of BestBench; ttheir
main purpouse seems to be Test bench generation.
Regards,
Konrad
--
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Konrad Feyerabend, Myliusstr. 36, 26135 Oldenburg, Tel 0441/ 27141
oder Konrad.F...@informatik.uni-oldenburg.de
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timo...@cyberramp.net
--snip--
> Unfortunately they do not
>provide evaluation copies (at least in Europe).
>I'm not sure on the documentation facilities of BestBench; ttheir
>main purpouse seems to be Test bench generation.
Accolade has a free demo CD that has a demo copy of Waveform Pro on
it. You can check out Accolade, and request your CD, at
http://www.acc-eda.com, and you can find Suncad (the Waveform Pro
people) at http://www.syncad.com.
Hope this helps.
Kevin Silver
In <328B8304...@prairiecomm.com> Lindo St Angel
<li...@prairiecomm.com> writes:
>
>I'm interested in finding out the relative merits of timing diagram
>editor tools like WaveformerPro from SynaptiCAD and TimingDesigner
from
>Chronology. We need a tool to analyze and document timing between
blocks
>at the system and unit levels. It would be nice if the tools can
>generate stimulus files in VHDL and/or Verilog for use in a testbench.
>It seems to me that WaveformerPro and TimingDesigner have about have
>about the same level of functionality, but the former is about half
the
>price. Has anyone looked at both of them? Which one is the better
value?
>Are there any other vendors I should be looking at?
>
>Thanks in advance.
>
Hi Lindo:
If you are looking for a tool that allows you to use timing diagrams
for: specification, design, analysis, and documentation of digital
circuits, then Chronology's TimingDesigner is your best bet. I know, I
worked in the
sales department at Chronology for over 3 years. I spoke with a LOT
of designers and had a LOT of good customers that are very happy with
TimingDesigner. Chronology has over 10,000 customers that are using
TimingDesigner since it's initial release ~6 years ago. I've sold
TimingDesigner to customers ranging from the big semi-houses like
Intel, AMD, TI, to one-man consulting firms. The things that my
customers really liked are:
TimingDesigner is a mature tool (10,000 users world-wide, ~6 years)
TimingDesigner runs on SUN, HP, and Windows(3.1, 95, and NT) (there are
even NEC, and Fujitsu versions in Japan)
TimingDesigner looks, feels, and acts identically across the variety of
platforms
In addition to single user licenses, a SUN, HP, or NT server can
"float" licenses to SUN, HP, and Windows(3.1, 95, or NT)
TimingDesigner is very easy to use and the documentation/support is
excellent; it has a complete on-line help, a nice printed users
manual(also available in pdf format), and a tool-free support line.
Another item that is very popular with TimingDesigner users is
Chronology's "Synchrony" program. The goal of the Synchrony program is
to work with the semi-houses to make "interactive timing diagrams"
available for commonly used parts. For example , TimingDesigner users
can download fully interactive timing diagram specs for Intels Flash
components directly from the Intel web site - for FREE. The nice thing
is that you can access component interface specs directly from the
vendors, and put them together in TimingDesigner to verfiy/optimize the
interface between your design and the surrounding components. The
TimingDesigner files from the vendors are usually "interactive" in that
they have created the diagrams with variables for things like clock
frequencies, wait states, etc; so you can instantly see how your design
responds to changes in clock frequencies or wait states just by
changing a single variable - it's pretty cool.
Sorry about the excess verbage (maybe I should go back into sales!).
Send me a line if you have any questions.
Sincerely, Kevin Silver.
Walter Banks
篠原 秀
We would like to implement small ROM into gates. What are the
good ways to do this in RTL? We would like to take advantage of
"don't cares" in both address and data.
Verilog has the "table" format in primitives.
Are there similar formats you can use in modules?
Thanks in advance.
Oleg Milter
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fatinell...@gmail.com
if VHDL is synthesis type .You could do VHDL to Verilog first and the look for a Verilog to C converter