How do I simulate two separate designs simutaneously in ModelSim XE?
Kevin Brace
Is there a way to do such a thing?
So far, I tried running two instances of ModelSim XE-Starter 5.5b, but
it won't let me run more than one instance of the program.
Actually, comparing the current waveform result with an already
simulated one saved to a file is adequate, but I have not been
successful doing that.
Thanks,
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Muzaffer Kal
<ihatespam99ke...@ihatespam99hotmail.com> wrote:
> I am trying to simulate two designs and compare the waveforms.
>Is there a way to do such a thing?
>So far, I tried running two instances of ModelSim XE-Starter 5.5b, but
>it won't let me run more than one instance of the program.
You don't need to run two instances. Just instantiate both designs in
a test bench and xor the outputs.
Muzaffer Kal
http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations
Egbert Molenkamp
to compare. Something like:
entity top is
port (input ??? where are the stimuli from?
match : out boolean)
end top;
architecture
your components
begin
instantiation1 : des1 port map (.., o11,o12, ..)
instantiation2 : des2 port map (.., o21, o22, ..)
match <= (o11=o21) and (o21=o22) --** (compare the outputs)
end.
Notice that the line with ** compares the output values at all time. Maybe
this is
not what is required. E.g. difference in delta delays may not be important.
In
that case you can write:
POSTPONED match <= (o11=o21) and (o21=o22)
If it is a synchronous system you probably want to check the outputs just
before the next active rising edge. This can be achieved with:
process
begin
wait until rising_edge(clock);
match <= (o11=o21) and (o21=o22)
end process;
Egbert Molenkamp
"Kevin Brace" <ihatespam99ke...@ihatespam99hotmail.com> wrote in
message news:a745ii$bo1$1...@newsreader.mailgate.org...
Utku Ozcan
> On Mon, 18 Mar 2002 01:47:13 -0600, Kevin Brace
> <ihatespam99ke...@ihatespam99hotmail.com> wrote:
>
> > I am trying to simulate two designs and compare the waveforms.
> >Is there a way to do such a thing?
> >So far, I tried running two instances of ModelSim XE-Starter 5.5b, but
> >it won't let me run more than one instance of the program.
>
> You don't need to run two instances. Just instantiate both designs in
> a test bench and xor the outputs.
Or just call the testbench twice in a much higher block "dummy":
module dummy ();
testbench tb_a ();
testbench tb_b ();
endmodule
But simulation will be twice slower, so why not running each of them
separately and then post-processing testvectors later on?
Utku
marc Nance
compare waveform files, but if your not of a mind to spend the extra
cash or if you dont need to do it that often, then one simple method
is to instantiate the two designs into the same testbench say as UUT1
and UUT2. you may need to duplicate the surrounding ics or have
separate copies of interface lines (as in addrbus1(15 downto 0) and
addressbus2(15 downto 0)).
It may run slower but it is possible to have two complete copies of
the design with two different UUTs burried in them.
If you want to get concerned about differences in operation or timing,
create a portion of the testbench that flags areas where the two dont
match or are different for more than X nS.
Kevin Brace <ihatespam99ke...@ihatespam99hotmail.com> wrote in message news:<a745ii$bo1$1...@newsreader.mailgate.org>...
Tom Loftus
The short answer is that there is a way to do that with Modelsim
but not with the limited XE-Starter version.
In the Modelsim SE 5.5a version I am using you can
do a "log" command and create a waveform database which by
default is called vsim.wlf. This seems to work the same
in the Starter edition.
After you finish your reference simulation, you could rename
this file, say "vsim_ref.wlf". Then, run a second simulation
and create another "vsim.wlf" file. Then, use the "Compare"
menu to compare and highlight discrepancies.
However, the XE/Starter edition I have doesn't have the "Compare"
menu option at all and trying to open a saved waveform file just
gives me a licensing error.
So, I think the other suggestions about trying to do it from
within a single simulation is your only option if all you have
to work with is the Starter version.
(Personally, I think comparing waveforms is a terrible way to
do verification but there seem to be many people who like to
do it.)
Tom
Kevin Brace <ihatespam99ke...@ihatespam99hotmail.com> wrote in message news:<a745ii$bo1$1...@newsreader.mailgate.org>...
Steve Meyer
feature by adding call "$dumpvars" to the design source (preferably at time
0 or if you do not want to compare results until a given time, at the at
that time). The first simulation will write verilog.dump file. After
simulation runs, copy file to other name and run model to compare again
with added $dumpvars. Then just use diff command to compare results.
It turns out that a given simulator will produce identical dumpvars file
providing wire declarations in two designs are same. This does not help
much in isolating differences. If you want to compare results from
different related designs or two different simulators, you need simple
program to compare dumpvars files. You can purchase fancy ones or you
can write one quite easily yourself.
Another standard P1364 approach is to use vpi_ and add value change call backs
(vpiValueChange) to signals of interest and have value change call back
routine just print time stamp and new value. You can then use various
unix tools to compare results.
/Steve
On Mon, 18 Mar 2002 01:47:13 -0600, Kevin Brace
<ihatespam99ke...@ihatespam99hotmail.com> wrote:
--
Steve Meyer Phone: (612) 371-2023
Pragmatic C Software Corp. email: sjm...@pragmatic-c.com
520 Marquette Ave. So., Suite 900
Minneapolis, MN 55402
Mike Treseler
> (Personally, I think comparing waveforms is a terrible way to
> do verification
I agree. Verification ought to be based on
expected results, not a "known good" piece of code.
This way you can print meaningful error messages
when there is a real problem and ignore irrelevant
waveform differences by default.
> but there seem to be many people who like to do it.
I think that many designers are tired of
looking at waveforms, but don't know
how to close the loop with testbench code.
-- Mike Treseler
Kevin Brace
Your solution was the best solution among the tips I got.
I will also like to thank everyone else for giving me various other
suggestions.
I may try out some of the suggestions later, but for the time being, I
wanted a quick fix type of solution that didn't take too much time to
implement.
So, following your advise, I created a new top module, and instantiated
the two modules, and compared the results.
In the process, I found why one of the design was finishing faster than
the other one.
I already knew that one of the design was finishing a bit faster than
the other one before I posted the question, but it was hard to pin point
the location where the one started to deviate from another.
Thanks,
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Kevin Brace
from a new top module, so I did that, and I finally figured out what was
going wrong.
I am pretty poor, so all I can afford is ModelSim XE-Starter, therefore
paying for the full version of ModelSim (PE or even XE) is not really an
option.
Thanks,
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Kevin Brace
>
> Kevin,
>
> The short answer is that there is a way to do that with Modelsim
> but not with the limited XE-Starter version.
>
> In the Modelsim SE 5.5a version I am using you can
> do a "log" command and create a waveform database which by
> default is called vsim.wlf. This seems to work the same
> in the Starter edition.
>
> After you finish your reference simulation, you could rename
> this file, say "vsim_ref.wlf". Then, run a second simulation
> and create another "vsim.wlf" file. Then, use the "Compare"
> menu to compare and highlight discrepancies.
>
> However, the XE/Starter edition I have doesn't have the "Compare"
> menu option at all and trying to open a saved waveform file just
> gives me a licensing error.
>
I didn't say it in so many words, but I did try open a .wlf file
which supposedly contains already simulated waveform information, but
each time I tried opening it, I also got licensing errors.
Do you know if this feature is disabled only in ModelSim XE-Starter, or
is it disabled in ModelSim XE which is a paid version?
Another thing I noticed was when I tried to open a .wlf file
with a ModelSim XE-Starter license that's fairly old, opening a .wlf
file caused a licensing error, but when I tried with a fairly new
license, I didn't get licensing errors, but I still couldn't figure out
how to open a .wlf file correctly.
I believe I got the old ModelSim XE-Starter license when the latest
version was 5.3, but I can be wrong with that (I don't remember when I
got the license.).
However, I got the the newer license after Xilinx started distributing
5.5b.
Your design environment sounds to me that you have access to a
full version at work (Modelsim SE 5.5a), but not at home or for personal
use, so you know something about the limitations of ModelSim XE-Starter.
Is that because of those license lock thing (flexlm) ModelSim uses? (I
guess that is pretty obvious.)
> So, I think the other suggestions about trying to do it from
> within a single simulation is your only option if all you have
> to work with is the Starter version.
>
Yes, I some other people also suggested that, so I tried it, and
it worked.
I had to make copies of some design files, and modify some .do files,
but I was still able to simulate both designs, and compared them.
> (Personally, I think comparing waveforms is a terrible way to
> do verification but there seem to be many people who like to
> do it.)
>
> Tom
>
Yes, I do understand that the method I used was not a very good
one (Wasn't this method called a golden vector method or something like
that? I believe I read that in Writing Testbenches by Janick Bergeron
some time ago.).
I am still in the process of implementing various features, so I am not
ready to spend serious amount of time in verification at this point, but
I still wanted to do some simple debugging, so that my design works, at
least partially.
After I finish the implementation, I am going to spend much more time in
verification.
Kevin Brace
alongside in a new top module, but I will remember that there are other
ways to compare waveform results.
When I was reading ModelSim's User Guide, I believe I read a section
that mentioned about VCD, but didn't want to spend a lot of time
learning more things because I wanted to quickly compare results.
I know not willing to learn new design approaches is fatal in
engineering, but for the time being, I wanted to compare waveform
results quickly because I am still at the the implementation stage of a
design, and not at the verification stage of a design yet.
Yes, when I reach the verification stage of my design, I will definitely
try to learn new verification methods, so that I can test my design
effectively.
Although I am sure some people don't like my "quick fix" type of
approach to testing.
Thanks,
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Steve Meyer wrote:
>
> One way to do the comparing is to add the P1364 standard dumpvars
> feature by adding call "$dumpvars" to the design source (preferably at time
> 0 or if you do not want to compare results until a given time, at the at
> that time). The first simulation will write verilog.dump file. After
> simulation runs, copy file to other name and run model to compare again
> with added $dumpvars. Then just use diff command to compare results.
> It turns out that a given simulator will produce identical dumpvars file
> providing wire declarations in two designs are same. This does not help
> much in isolating differences. If you want to compare results from
> different related designs or two different simulators, you need simple
> program to compare dumpvars files. You can purchase fancy ones or you
> can write one quite easily yourself.
>
> Another standard P1364 approach is to use vpi_ and add value change call backs
> (vpiValueChange) to signals of interest and have value change call back
> routine just print time stamp and new value. You can then use various
> unix tools to compare results.
> /Steve
>
>
Kevin Brace
and run both of them from a top module.
I guess your idea will be to XOR the outputs coming from the two modules
to see when they won't match.
I guess that is possible in theory, but I rather see both waveforms
untouched myself.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Tom Loftus
Please see embedded responses to the questions
you raised.
Kevin Brace wrote:
> <snip>
> I didn't say it in so many words, but I did try open a .wlf file
> which supposedly contains already simulated waveform information, but
> each time I tried opening it, I also got licensing errors.
> Do you know if this feature is disabled only in ModelSim XE-Starter, or
> is it disabled in ModelSim XE which is a paid version?
I don't know.
> <snip description of other licensing stuff>
> Your design environment sounds to me that you have access to a
> full version at work (Modelsim SE 5.5a), but not at home or for personal
> use, so you know something about the limitations of ModelSim XE-Starter.
That's correct.
>
> Is that because of those license lock thing (flexlm) ModelSim uses? (I
> guess that is pretty obvious.)
>
You answered your own question.
> Yes, I do understand that the method I used was not a very good
> one (Wasn't this method called a golden vector method or something like
> that? I believe I read that in Writing Testbenches by Janick Bergeron
> some time ago.).
> I am still in the process of implementing various features, so I am not
> ready to spend serious amount of time in verification at this point, but
> I still wanted to do some simple debugging, so that my design works, at
> least partially.
> After I finish the implementation, I am going to spend much more time in
> verification.
I don't really want to turn this into a big thread on
the pros and cons of waveform comparison as a verification technique so I
think I will drop this right here.
Tom
Petter Gustad
> I am trying to simulate two designs and compare the waveforms.
> Is there a way to do such a thing?
Why not instantiate the two DUTs and compare the output cycle by
cycle? You could then generate some nets which gets asserted whenever
two signals are different.
Design Acceleration (now part of Cadence) has a product called
comparescan for this purpose.
Petter
--
________________________________________________________________________
Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.com
Petter Gustad
> Other people recommended instantiating two designs in one top module,
> and run both of them from a top module.
> I guess your idea will be to XOR the outputs coming from the two modules
> to see when they won't match.
> I guess that is possible in theory, but I rather see both waveforms
> untouched myself.
You can still dump the entire hierarchy from the DUTs and below (I
would include the compare module as well) so both your waveforms will
be untouched.
I usually sample the outputs and do a plain compare far out in the
cycle.
Petter Gustad
> One way to do the comparing is to add the P1364 standard dumpvars
> feature by adding call "$dumpvars" to the design source (preferably at time
> 0 or if you do not want to compare results until a given time, at the at
> that time). The first simulation will write verilog.dump file. After
> simulation runs, copy file to other name and run model to compare again
> with added $dumpvars. Then just use diff command to compare results.
Clever!
Petter Gustad
> Design Acceleration (now part of Cadence) has a product called
> comparescan for this purpose.
Comparing waveforms that is, not instantiating the two DUTs.
With signalscan (waveform viewer) you can easily open two TRN (trace
files generated by the signalscan PLI routines or converted from VCD)
from two different simulations. You can also specify an event search
to find where they differ.
Robert Schopmeyer
Compare Scan just to compare your waveform files. You have with
Undertow three different ways to allow you to compare files. Note that
these files can be of any format, wlf, vcd, compressed, any format
that Undertow can read, and this tool can read almost every single
format from every commercial simulator on the market today. You can
compare files even if they have completely different formats.
Using Test Analyzer, a tool on Undertow, you can compare two different
files, with the differences showing up on the waveform window as a
plumb colored back ground over the area of the signal that is
different. You can specify the start and end time for the compare, the
signals to be compared and a clock with a window on the trailing or
leading edge of this clock for this comparison.
Using the "Overlay feature" you can overlay three separate files. The
resulting waveform will be orange if the signal area is the same, and
yellow where they are different.
Using the built in Perl scripting tool, and then the
compare_file.script which is one of the many several dozen scripts
that come with Undertow. With this script, you can do a compare as a
batch or interactive process. On very large designs this script can be
run without a GUI in a batch process, against files that may be many
gigabytes in size. These scripts have been designed to work at very
high speeds, hundreds of thousands of times faster than just plane
generic Perl. Since the Perl script source code is included in the
Undertow distribution, you can quickly modify this code in any way you
wish to change the behavior of the exact compare operation. For
example, you can allow jitter for a set of signals, or allow a
difference threshold before indicating a mismatch, etc. Every single
possible compare operation that you can do manually, you can do using
this built in Perl scripting capability.
You can get Undertow from www.veritools-web.com, and send a request to
sc...@veritools.com, in order to get a no cost license to use this
software. Regards,
Robert Schopmeyer/Veritools, Inc.
Petter Gustad <newsma...@gustad.com> wrote in message news:<87it7s1...@filestore.home.gustad.com>...