function overloading in vhdl
vipin lal
I want to do function overloading in one of my designs.I googled for
some examples and I learned that for function overloading to work, you
need either different number of parameters or different type of
parameters.
But I want something like this in my code:
function f(a : in std_logic_vector(1 downto 0)) return std_logic is
....
end f;
function f(b : in std_logic_vector(2 downto 0)) return std_logic is
....
end f;
The only change is that a is 2 bit in size and b is 3 bit in size. How
do I do something like this. Is there any hack to get this kind of
thing working?
Thanks
vipin
Jonathan Bromley
> do I do something like this. Is there any hack to get this kind of
> thing working?
No hack required; instead, you can tap in to one of the
very best features of VHDL: unconstrained subprogram parameters.
Just use ordinary array attributes to inspect the argument
you have been given.
function f (in v: std_logic_vector) -- NO SIZE HERE!
return std_logic_vector is -- NO RESULT SIZE!
constant msb: integer := v'left;
constant lsb: integer := v'right;
constant size: integer := v'length;
variable normalized_v: std_logic_vector(size-1 downto 0);
variable result: std_logic;
begin
normalized_v := v; // avoid slice-direction trouble
result := v(msb) xor v(lsb);
return result & normalized_v(size-2 downto 0);
end;
OK, the code is silly, but you see what I mean - this function
returns a vector that's the same as its input vector, but with
the MSB replaced with the XOR of the original MSB and LSB.
Love it. Eat your heart out, Verilog.
--
Jonathan Bromley
KJ
You don't need to overload the function call at all in your instance
function f(a : in std_logic_vector) return std_logic is
begin
if (a'length = 2) then
...
elsif (a'length = 3) then
...
else
...
end if;
end function f;
KJ
vipin lal
details about the module I want to design.
The size of the input parameter(std_logic_vector) is a generic
value.So if I write the function as KJ mentioned, then I will be
wasting resources,I think.
Thats why I want separate functions and these functions I will put it
in a package.This will ensure that only required logic is implemented.
The functions should look like this:
function f(a : in std_logic_vector(1 downto 0)) return std_logic is
output := some xor operations between the bits of 'a'.
end f;
function f(b : in std_logic_vector(2 downto 0)) return std_logic is
output := some xor operations between the bits of 'b'.
end f;
Here the logic inside each function is different.Also size of signal a
or b is a generic parameter.So I will be using only one function when
synthesising the function for a device.
Thanks
vipin
Tricky
Synthesisors are pretty good at minimising resource usage for you.
Best thing about this: write easy to understand functions - let
synthesisors do the hard work.
Unless you need the function to be very different for each value of
the generic. In this case, KJ's option is probably the only way to do
it. In this case, unused paths in the function (because the length is
fixed) will be ignored.
vipin lal
Ok, I will try KJ's method and see if it generates extra logic or not.
Thanks
vipin
Andy
>
> Synthesisors are pretty good at minimising resource usage for you.
> Best thing about this: write easy to understand functions - let
> synthesisors do the hard work.
>
Agreed whole-heartedly! Since the length of a vector argument is
"static" in the synthesis realm (determinable when the synthesizer
runs), it gets treated like a constant, and optimized away. The if
statements that are false for any given invocation of the function get
pruned. Whether the tool shows you this in its "RTL" schematic view,
or in its "Technology" schematic view, it gets pruned eventually.
The same thing is true with for-loop indices. Since the bounds of
synthesizeable loops must be static (loops are unrolled in synthesis),
the index is treated as static for each trip through the loop.
Andy