force vs. assign
Sashi Obilisetty
>
>What's the difference between force and assign when applied to a register?
>
>Daniel
>--
>Daniel S. Barclay Compass Design Automation, Inc.
>dan...@compass-da.com Suite 101, 5457 Twin Knolls Rd. Columbia, MD 21045 USA
> "They listen hard, and act like they care.
> How can they be so completely unaware
> Of the truth? The answer is always denied me
> So I introduce 'em to the killer inside me." - MC 900-Foot Jesus
registers can only take the 'assign' procedural continuous assignment.
'force' is used on nets.
--
* Sashi Obilisetty *
* Alternative System Concepts, Inc. *
* PO Box 128 Windham NH 03087 *
* tel (603) 437-2234 fax (603) 437-ASC2 URL http://www.ascinc.com *
Daniel S. Barclay
Michael McNamara
In article <DANIEL.95N...@arcturus.compass-da.com>
dan...@compass-da.com (Daniel S. Barclay) asks:
What's the difference between force and assign when applied to a register?
Not much except that the force is supposed to be ``stronger'' than the
procedural continuous assignment.
Just another logical verifier...
-mac
[mailed & posted]
--
Michael McNamara
Verilog-HDL Consulting Services, Inc.
Daniel S. Barclay
> ..
>
> 'force' is used on nets.
IEEE draft Verilog says otherwise (note the force and release cases for
registes):
procedural_continuous_assignment ::=
"assign" reg_assignment ";"
| "deassign" reg_lvalue ";"
| "force" reg_assignment ";"
| "force" net_assignment ";"
| "release" reg_lvalue ";"
| "release" net_lvalue ";"
Does this apply only to IEEE draft standard Verilog?
Darren Lasko
1) Use the blocking ( = ) or non-blocking ( <= ) procedural assignment. For
this, you don't use the "assign" keyword, you just say:
a <= b ;
This type of assignment is NOT continuous, it just updates the value in
the reg at the time the statement is executed.
2) Use the "procedural continuous assignment" with the "assign" keyword.
This acts just like a continuous assignment statement for nets, but you
use it in an "initial" or "always" block on a reg. A procedural continuous
assignment will override any procedural assignment (see 1, above) on
that reg until simulation reaches a "deassign <reg>" statement. For this
type of procedural continuous assignment, you would use a statement like
this:
assign a = b ;
Where "a" is of type reg. "b" can be any valid expression. Also, since
"a" is of type reg, this statement must be in an "initial" or "always"
block. If at some time in your simulation you want to stop the
continuous assignment to "a", you would use the following statement:
deassign a ;
3) Use the "procedural continuous assignment" with the "force" keyword.
This is just like (2), except that it not only overrides procedural
assignments (see 1, above), it also overrides procedural continuous
assignments that used the "assign" keyword (see 2, above). You usually
don't use the "force" keyword in verilog code, it's main function is to
"patch" signals during debug while using the simulator in interactive
mode. For this type of procedural continuous assignment, you would use a
statement like this:
force a = b ;
Where "a" is of type reg OR net. "b" can be any valid expression. If at
some time in your simulation you want to stop the continuous assignment
to "a", you would use the following statement:
release a ;
I hope this clears things up for you.
-Darren
In article <DANIEL.95N...@arcturus.compass-da.com>,
Daniel S. Barclay <dan...@compass-da.com> wrote:
>
>What's the difference between force and assign when applied to a register?
>
Darren Lasko
Sashi Obilisetty
>> >
>> >What's the difference between force and assign when applied to a register?
>>
>> 'force' is used on nets.
>
>IEEE draft Verilog says otherwise (note the force and release cases for
>registes):
>
> procedural_continuous_assignment ::=
> "assign" reg_assignment ";"
> | "deassign" reg_lvalue ";"
> | "force" reg_assignment ";"
> | "force" net_assignment ";"
> | "release" reg_lvalue ";"
> | "release" net_lvalue ";"
>
>
>Does this apply only to IEEE draft standard Verilog?
>
>Daniel
>--
No, and your interpretation is right. Change that to
force-release can be applied to nets as well.
The other replies to your query must have cleared
up the matter for you.