verilog-A or VHDL-AMS ?
Julien Charton
Dear friends,
I need to choose a HDL to build macro-models of Micro-Electro-Mechanical
(MEMS)
actuatuators.
- What are the difference between VHDL-AMS, Verilog-A or other languages
such as MAST ?
- Is there another forum or newsgroup more specifically focused on
analog HDLs ?
Regards,
julien
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Julien Charton "Simplicity should be the
CNRS-LAOG goal of sophistication"
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Steve Hamm
Julien Charton <cha...@obs.ujf-grenoble.fr> writes:
> - What are the difference between VHDL-AMS, Verilog-A or other languages
> such as MAST ?
This can easily get into the usual Verilog/VHDL religious wars, but...
Verilog-A is the analog-only subset of the Verilog-AMS language, which
is an OVI standard (OVI is now Accellera: www.accellera.org) but not
(yet) an IEEE standard. Verilog-AMS differs from VHDL-AMS in that an
analog-only subset is defined, suitable for implementation in
conjunction with a SPICE-like simulator, which is helpful for strictly
analog high-level modeling tasks.
VHDL-AMS is an IEEE standard, extending VHDL into continuous-time
simulation. VHDL-AMS keeps the flavor of VHDL, which is good or bad
depending on whether one likes VHDL. Since there is no analog subset,
a VHDL-AMS implementation must include a digital simulator.
Verilog-A doesn't stray far from the circuit simulation background
from which it evolved, so the semantics may be fairly easy for
electrical engineers. VHDL-AMS looks to me more like some of the
general continuous system simulation languages, and often takes a bit
more language to do some things. Ultimately, either can be made to do
the job. In practice, I believe most people will find Verilog-A
easier to use, but then I'm a bit prejudiced as I've worked with
Verilog-A quite a bit.
There are, to my knowledge, nearly four commercial implementations of
Verilog-A/AMS available (currently from Antrim and Cadence; soon from
Synopsys and Mentor/Anacad), and no free implementations.
For VHDL-AMS, there are three commercial implementations (from
Mentor/Anacad, Avanti/Analogy, and SIMEC (www.hamster-ams.com)) and
one free implementation (SEAMS from Univ. of Cincinnati). I've tried
none of these, so I have no idea how real these are.
MAST is proprietary to Avanti/Analogy and is a mature product. The
language is considered difficult by some. Since MAST is proprietary
and Avanti/Analogy supports VHDL-AMS, I expect that MAST usage should
disappear as time goes on...
> - Is there another forum or newsgroup more specifically focused on
> analog HDLs ?
If there is, I am not aware of it.
--Steve
Thierry Villard
It can be tested on http://www.dolphin.fr/medal/smash/smash_overview.html
Thierry
Kevin Cameron
The people responsible for MAST were the prime developers of VHDL-A. VHDL-AMS
is a kludgy combination of analog and digital simulation. As said above, Verilog-A is a purely analog
subset of Verilog-AMS - a less kludgy mixed-signal language, but still a work in progress
(thanks to Cadence's slow going).
Links for Verilog-AMS:
http://www.eda.org/verilog-ams/ < Accelera Committee pages (old)
http://www.accellera.org/
http://groups.yahoo.com/group/acc-tc-v-ms < Open discussion (moderated)
NB: more participation by (potential) users of Verilog-AMS in the Accellera languge development
committee will help the EDA companies involved get a good product out there sooner.
Personnally I would not recommend VHDL-A for mixed-signal design as the simulation semantics
are (IMO) broken and unreliable.
Regards,
Kev