How to define a text macro that concatenates two strings in Verilog?

[carl.h...@gmail.com]

I am trying to concatenate two strings with `define macro definition, it does not work. Any help would be greatly appreciated.

module tb;

`define ROOT_DIR "C:/tmp
`define MYFILE `ROOT_DIR/mysigfile.txt"

reg clk;
integer fh_testsig;

initial begin
clk = 0;
fh_mysigfile = $fopen(`MYFILE, "w");
end

always #5 clk = ~clk;

always @ ( posedge clk) begin
$fwrite(fh_mysigfile, "%1b\n", clk);
end

endmodule

-Carl

[Gabor]

After changing fh_testsig to fh_mysigfile in your example, it works
fine in ISIM. It created a file c:\tmp\mysigfile.txt, and printed
a pile of 1's in it.
What simulator are you using?

-- Gabor

[carl.h...@gmail.com]

Thanks Gabor,

Yes, I had a typo. And, yes, it works for ISIM. With ModelSim, it errors out with the following message:

# ** Warning: test.v(5): (vlog-2269) Unterminated string literal continues onto next line 5.
# ** Error: test.v(13): (vlog-2163) Macro `MYFILE is undefined.
# ** Error: C:/modeltech64_10.0b/win64/vlog failed.
# Error in macro ./tb.fdo line 23
# C:/modeltech64_10.0b/win64/vlog failed.
# while executing
# "vlog "test.v""

Any idea to make it work for both ISIM and ModelSim?

The corrected test verilog code is re-posted here:

`timescale 1ns / 1ps

module tb;

`define ROOT_DIR "C:/tmp
`define MYFILE `ROOT_DIR/mysigfile.txt"

reg clk;

integer fh_mysigfile;

initial begin
clk = 0;
fh_mysigfile = $fopen(`MYFILE, "w");
end

always #5 clk = ~clk;

always @ ( posedge clk) begin
$fwrite(fh_mysigfile, "%1b\n", clk);
end

endmodule

Line 5 is: `define ROOT_DIR "C:/tmp

[Gabor]

This works in ISIM and Compiles in Modelsim, but for some reason I'm
having license issues so I couldn,t see if it works in Modelsim:

module tb;

parameter ROOT_DIR = "C:/tmp";
parameter MYFILE = "/mysigfile.txt";

reg clk;
integer fh_mysigfile;

initial begin
clk = 0;

fh_mysigfile = $fopen({ROOT_DIR,MYFILE}, "w");

end

always #5 clk = ~clk;

always @ ( posedge clk) begin
$fwrite(fh_mysigfile, "%1b\n", clk);
end

endmodule

Apparently Modelsim parses quotes before it runs the preprocessor. I'm
not sure if this is covered in the LRM, but my guess is that it's an
unusual usage of a macro in your case. My changes use parameters
instead of macros, and for those the standard concatenation seems
to work.

-- Gabor

[carl.h...@gmail.com]

Thanks Gabor, Could you please give me a hint on how this can be done with parameter? - Carl.

[carl.h...@gmail.com]

I am so sorry that I did not see that you had given me the complete code to show its working with "parameter". I really appreciate your spending time helping me on this. Thanks so much!

[Gabor]

carl.h...@gmail.com wrote:
> I am so sorry that I did not see that you had given me the complete code to show its working with "parameter". I really appreciate your spending time helping me on this. Thanks so much!

I'm still fighting with my Modelsim license... Did the code
work for you?

-- Gabor