Syntax error in Verilog task
Verictor
What is wrong with the integer i defined in the following task?
task delimited_out;
input [width-1:0] a; // width has been defined
somewhere else
input delimiter_width;
integer i;
begin
for (i = 1; i <= width/delimiter_width; i = i + 1)
begin
$display("the delimited_out is %b_", a[width-
delimiter*(i-1)-1 : width-delimiter*i]);
end
end
endtask
Compiler complains that "Illegal operand for constant expression for
i".
Thanks
John_H
news:1177602837....@r3g2000prh.googlegroups.com...
The problem is with the a[width-delimiter*(i-1)-1 : width-delimiter*i]
syntax.
While it looks like it should work by providing a constant width, it's not
valid Verilog.
It also appears you intend to use "delimiter_width" rather than "delimiter."
Verilog2001 allows a syntax that will probably work in your case:
a[width-delimiter*i +: delimiter_width]
The constant width expression - delimeter_width - is now obvious to the
Verilor2001 synthesizer and no syntax errors should be flagged. If this
form is not acceptable to you, insert a second loop to do the bit
assignments one by one, not specifying ranges.
- John_H
gabor
> "Verictor" <stehu...@gmail.com> wrote in message
or perhaps a little more readable?
for (i = delimiter_width; i <= width ; i = i + delimiter_width)
. . . a[i +: delimiter_width] . . .
Verictor
>
> - Show quoted text -
what simulators are you guys running? I used the two versions you
suggested above but still get "Illegal operand for constant
expression" on delimiter_width (both codes). I am using NC-Verilog.
John_H
Is the delimeter_width a constant? If so, the value should not be an
"input" as shown in your port list but a "parameter" instead.
If you're not dealing with a constant, you may be able to get where you want
to be by coding bit by bit but the logic feeding into any one bit will be
gnarly: not pretty. A constant value is probably what you want which will
make the coding clean. I certainly prefer gabor's readability compared to
the original form of the code.
- John_H