ModelSim Synchronizer
Rob
I have a clock signal coming into my FPGA. It is a slow clock (10kHz)
that drives a state machine. I want to bring it into another clock
domain by using a 3 flops in a row like shift register. The clock
driving the sync flops is much faster (90MHz).
I am actually running a gate level simulation (Altera Cyclone 3).
ModelSim tells me I have timing violations on the first flop in the
synchronizer, which is to be expected. But the remaining flops in the
sync circuit will move this async signal into the new domain and should
eliminate metastability and setup/hold violations. But when these timing
violations occur MS puts an unknown value at those positions which
affects all of the logic on the output of the synchronizer. Which in
turn screws up my state machine.
Can anyone offer up a suggestion on how to better setup MS under these
circumstances?
Thank you,
Rob
Kim Enkovaara
> eliminate metastability and setup/hold violations. But when these timing
> violations occur MS puts an unknown value at those positions which
> affects all of the logic on the output of the synchronizer. Which in
> turn screws up my state machine.
>
> Can anyone offer up a suggestion on how to better setup MS under these
> circumstances?
Just use tcheck_set command, in your case it is something like this:
tcheck_status my.instance
There you can see the timing checks in correct format and you can
copypaste it to the next line
tcheck_set my.instance ( the SDF rule that is configured) on off
Or if you are not that interested in timing violation X:s put
+no_notifier command line option to vsim command. These are
quite well covered in the manuals.
--Kim
Muzaffer Kal
This is not specific to modelsim but you can always go into the SDF
file and make the setup/hold values for the first synchronizer
register to 0 to disable them. This way there will not be any timing
violations for that register to propagate to the next synchronizers.
To make sure that you are not depending this perfect behaviour you can
also make a custom DFF gate level model (ie copy the gate level model
of the first flop, rename it and change it) to output random values
instead of the exact values.
--
Muzaffer Kal
DSPIA INC.
ASIC/FPGA Design Services