You could log the signal, then use the "examine -time" command in a
Tcl script to read the data out of the waveform log at specified
times. Tcl could easily write out these values as a .csv or
similar file.
However, it would probably be both easier and more elegant to get
Verilog to write out the .csv file for you, using $fdisplay.
That way, you could easily save data per-clock, per-transaction
or on-change. Something like this (in your top-level
test fixture):
initial begin: CSV_Dump
integer csv; -- ID of CSV file
f = $fopen("somefile.csv");
if (!f) begin
$display("Couldn't open CSV file");
$stop;
end
// Wait for reset to go away:
@(negedge reset);
// Assumes there's a signal called "running" in the
// test bench, which is true at the start and goes
// false when simulation is finished
while (running) @(posedge clk or running) begin
$fdisplay(f, "%0d,%0d,%0d", $time, dataIn, dataOut);
end
// ok, simulation is done, close the output file:
$fclose(f);
end // CSV_Dump
Not tested, not carefully proof-read, but I hope you can
see the general idea.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
You could try $monitor and insert tabs appropriate positions.
Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Jonathan Thanks for the example!! I was struggling with the same issue
that DW was. Here is what worked for me. I had to change line 2.
//888888888888888888888888888888888888888888888888888888888888888888
// OUTPUT SIM RESULTS TO FILE
//888888888888888888888888888888888888888888888888888888888888888888
// the following must be in your signal declarations.
// reg reset_n;
// reg running;
// also drive these signals in the appropriate
// section of your file. ex:
// initial begin
// clk = 0;
// data_in = 0;
// reset_n = 0;
// #10 reset_n = 1'b1;
// en = 'b1;
// running = 1'b1;
// end
//88888888888888888888888888888888888888888888888888888
// start of file
//88888888888888888888888888888888888888888888888888888
initial begin: CSV_Dump
integer f; // ID of CSV file
f = $fopen("outdata.csv");
if (!f) begin
$display("Couldn't open CSV file");
$stop;
end
// Wait for(active low) reset to go away.
// you must have this signal defined in the testbench.
@(posedge reset_n);
//Assumes there's a signal called "running" in the
// test bench, which is true at the start and goes
// false when simulation is finished
while (running) @(posedge clk or running) begin
$fdisplay(f, "%0d,%0d,%0d", $time, data_in, data_out);
end
// ok, simulation is done, close the output file:
$fclose(f);
end // CSV_Dump
//8888888888888888888888888888888888888888888888888888888888888888
// CSV_Dump
//8888888888888888888888888888888888888888888888888888888888888888