Split bus notation in verilog

[rcg007]

Hi,
I have a design block which has input of 128 bits. A bus of 256 bits has to
be connected to this input by taking only the even bits or the odd bits. Is
there a way to represent this in verilog?

I am talking about a notation like this in Cadence
BUS[254:0:2]. Is there a similar representation in Verilog?

Thanks in advance,
-rcg007

[John_H]

Do you want a registered mux?

reg [127:0] bus2block;
integer i;
always @(posedge clock)
for(i=0;i<128;i=i+1)
bus2block[i] <= odd_not_even ? in_bus[2*i+1] : in_bus[2*i];

Do you want a combinatorial mux?

reg [127:0] bus2block; // this is really a combinatorial value because
the always is unclocked
integer i;
always @(odd_not_even or in_bus)
for(i=0;i<128;i=i+1)
bus2block[i] = odd_not_even ? in_bus[2*i+1] : in_bus[2*i];