How to divide a frequncy/Clock by 3

[Yi-Ran Wang]

How to divided a frequency or Clock by 3,5,6....10 using Flip flop? I tried
to use counter but I don't know how to stop at 3,5,6...or 10. Please tell me
how to connect them physically. Thanks!

[Jim]

Dividing a clock by an even number and getting a 50% duty cycle clock output
is trivial (invert you clock output every time the counter reaches half of
the divider and reset the counter). It is not as easy for odd dividers. But
for the particular ones (3 and 5) you want, Xilinx has an app note showing
how to get 50% duty cycle output with combinatorial logic. Here is the URL
http://www.xilinx.com/xcell/xl33/xl33_30.pdf But if you are using PLL or
DLL, you do not have to do all this.

Hope this helps.
Jim

"Yi-Ran Wang" <ianw...@sbcglobal.net> wrote in message
news:ndWK7.285$564.21...@newssvr21.news.prodigy.com...

[Shai Eshet]

here is the implementation in verilog.

module clkdiv3(clk,clkout);
input clk;
output clkout;

reg [1:0] count;
reg       sig1;
reg       sig2;

always @(posedge clk)
 begin
   count <= count + 1;
   if (count == 2)
       count <= 0;
 end

always @(count)
  begin
    if (count == 0)
        sig1 = 1;
    else
        sig1 = 0;
  end

always @(negedge clk)
  begin
    sig2 <= sig1;
  end

assign clkout = sig2 | sig1;
endmodule

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[Illan]

Hi,
you might prefare the following that have less logic on the clock
and thus less sqew from the master clock which in some case might make
effect.

always @ (posedge clk or negedge rstn)
if (~rstn)
sr <= #1 3'b100;
else
sr <= #1 {sr[1:0],sr[2]};

than the clock is any of the bit you choose from sr for example

assign clk_div3 = sr[0];

for higher divider you can than combine the counter with sr of 2 or 3
etc and get the dived clock with reasnbale amount of FF and with good
sqew. (for example if need to devide by 24 make a counter to 12 and sr
of 2 bit)

have a nice day

Illan

Shai Eshet <sh...@silicon-value.com> wrote in message news:<3C05F000...@silicon-value.com>...

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