Edge detection logic

[Chun-Hung Lin]

Dear Group

How do I write a "Edge Detection Logic"?
1. Detect a rising edge or falling edge of a signal, such as an event
detection for interrupt triggering.
2. Once an edge has been detected, it will be stored in a register.
3. A clear signal is required to clear the register.

I am thinking about using the signal pin as a clock.
However, it does not seem to work. What is wrong?

Thanks in advance.

Chun-Hung Lin
chli...@my-deja.com

assign nsignal = ~signal;
always @(posedge signal or negedge nclear)//rising edge
begin
if(~nclear)//clear interrupt
r_status_reg <= 1'b0;
else
r_status_reg <= 1'b1;
end

always @(posedge nsignal or negedge nclear)//falling edge
begin
if(~nclear)//clear interrupt
f_status_reg <= 1'b0;
else
f_status_reg <= 1'b1;
end

[Sanjay Kumar Sharma]

Hi,

You don't have to use that signal as a clock pin. However you need a
clock to delay that signal and then XOR that signal with the delayed one
to capture rising and falling edges.

something like..
always @ (posedge clk)
if (clk)
delayed_signal <= signal_in;
end

edge_signal <= signal_in xor delayed_sig.

ps: edge_signal will go high whenever there is a rising oir falling edge
on this signal.

Sanjay Sharma

Agere Systems
System on Chip IC Designer
3G Wireless Mobile Application
Allentown, PA

[Chun-Hung Lin]

Hi, Sanjay and dear group:

Thanks a lot.

One more question, how do I detect rising and falling edge separately?
Thanks in advance.

Chun-Hung Lin

Sanjay Kumar Sharma <sanjay...@agere.com> wrote in message news:<3B963239...@agere.com>...

[Muzaffer Kal]

chli...@my-deja.com (Chun-Hung Lin) wrote:

>Hi, Sanjay and dear group:
>
>Thanks a lot.
>
>One more question, how do I detect rising and falling edge separately?
>Thanks in advance.
>
>Chun-Hung Lin
>
>
>Sanjay Kumar Sharma <sanjay...@agere.com> wrote in message news:<3B963239...@agere.com>...
>> Hi,
>>
>> You don't have to use that signal as a clock pin. However you need a
>> clock to delay that signal and then XOR that signal with the delayed one
>> to capture rising and falling edges.
>>
>> something like..
>> always @ (posedge clk)
>> if (clk)
>> delayed_signal <= signal_in;
>> end
>>
>> edge_signal <= signal_in xor delayed_sig.

a posedge is where the delayed signal value is 0 and the current value
is 1 so you can say:

posedge_signal <= signal_in and (not delayed_sig).

conversely for negedge the current value should be zero and the
previous value should be one:

negedge_signal <= (not signal_in) and delayed_sig.

Muzaffer
http://www.dspia.com

[brijesh...@gmail.com]

Dear Mr.Chin-Hung,

I hope you're doing good.I am currently pursuing my Master's In Electrical Engineering and learning FPGA this semester. I understood the concept of Falling Edge & Rising Edge & how to implement with Quartus II.Now i want to implement both rising & falling edge detection at same time,can you help me out to do the same.



Thank you in advance for your time & consideration.


Regards,
Brijesh Darji
linkedin.com/in/darjibrijesh

[rickman]

Is this something you will use in a test bench? There is no hardware
that corresponds to a dual edge detection, so such logic will not be
synthesizable.

--

Rick

[Johann Klammer]

On 01/28/2016 04:07 AM, rickman wrote:
>
> Is this something you will use in a test bench? There is no hardware that corresponds to a dual edge detection, so such logic will not be synthesizable.
>

He could use 2 FFs and or the outputs

[rickman]

That is not really "dual edge detection" in that it will produce two
signals that will need to be combined in some relevant manner. I'm not
sure any arbitrary logical function using two clock edges can be
reproduced with two separate FFs.

--

Rick