Overriding `define s in Verilog

[Srinivasan Venkataramanan]

Hi,
Perhaps it is very simple to do, but I am not that much used to Verilog
yet. Please help (if possible please put me on CC while replying)

Thanks in advance.

Srini

venkataraman...@philips.com

===========

In my memory models my vendor puts a line as

`define DEBUG 1

`ifdef DEBUG
$display("Error in address...") ;
`endif

I hate receiving these messages b'cos I know that the address is not valid
before reset etc. I found a way to get rid of these messages, by commenting
out these lines, but obviously this is not the best solution. Is there any
elegant wat to do this? say can I override these "`defines" externally??

=====================

[Sudhir Kadkade]

Srini,
It depends on the simulator you are using; in Verilog-XL you can
define compiler directives by using the +define command line
switch. For example - verilog +define+FOOBAR -f sim.vc;
FOOBAR is defined for the simulation.

Regards,
Sudhir

[Srinivasan Venkataramanan]

Hi Sudhir,
I know how to "define", but I want to know "How to Undefine".
Please help.

Thanks for the reply.

Regards,
Srini

Sudhir Kadkade <Sudhir_...@SiFR.com> wrote in message
news:83gia3$u0k$1...@nntp5.atl.mindspring.net...

[Mike Hardy]

You could include with your compile line +define+DEBUG=0 (check syntax)
which I believe overrides the defines in the code (at least with VCS).

--

--------------------
Mike Hardy
har...@earthlink.net

Real Engineers:

Wear badges so they don't forget who they are. Sometimes
a note is attached saying "Don't offer me a ride today. I
drove my own car."

[Sudhir Kadkade]

Srini,
The only way I know to undefine something is through the `undef
directive. You could conditionally include a `undef DEBUG after
the `define DEBUG, and control this from the command line.

BTW, the suggestion by Mike Hardy - +define+DEBUG=0
to undefine DEBUG, does not work with Verilog-XL.

Regards,
Sudhir

Srinivasan Venkataramanan wrote in message
<83gmm5$27n7$1...@news4.isdnet.net>...

[Srinivasan Venkataramanan]

Hi Sudhir,
Thanks again for trying to help me out here, especially for
trying the suggestion from Mike. It is really kind of you.

Your solution doesn't solve my problem as I still have to edit the
Verilog model - which is the last thing that I would do(but currently that'
what I am doing (:- ) . I read some where that "parameter"s could be
overridden externally, is this true? If so, couple of questions related to
this:

1.> If parameters are configurable/modifiable at top why not `define s? Is
this a requested enhancement for up-coming Verilog standard by any chance?

2.> Can I use parameters to check in the " `ifdef line" - I understand that
this sounds stupid as the name sugegsts "if defined" and I can imagine
"define" is only thorugh "`define", nevertheless nothing harm in getting it
clarified from experts.

Thanks again.

P.S. I am using Verilog-XL

Kind Regards,
Srini

Sudhir Kadkade <Sudhir_...@SiFR.com> wrote in message

news:83hcpp$f5p$1...@nntp5.atl.mindspring.net...

[Puneet Goel]

Hi Srini

It is not a very elegant solution but should work :)

verilog <your options> <your files> | grep -v "Error in address..."

- regards

--
Puneet Goel
email - puneet at computer period org
home - (91)124-335056
work - (91)124-303212 x 1213
--
GOD comes to me in the dusk of my
evening with the flowers from my
past kept fresh in his basket.
- Rabindranath Tagore (Stray Birds)
--

>>>>> "SV" == Srinivasan Venkataramanan
>>>>> <venkataraman...@philips.com> writes:

SV> Hi, Perhaps it is very simple to do, but I am not that much
SV> used to Verilog yet. Please help (if possible please put me on
SV> CC while replying)

SV> Thanks in advance.

SV> Srini

SV> venkataraman...@philips.com

SV> ===========

SV> In my memory models my vendor puts a line as

SV> `define DEBUG 1

SV> `ifdef DEBUG
SV> $display("Error in address...") ;
SV> `endif

SV> I hate receiving these messages b'cos I know that the address
SV> is not valid before reset etc. I found a way to get rid of
SV> these messages, by commenting out these lines, but obviously
SV> this is not the best solution. Is there any elegant wat to do
SV> this? say can I override these "`defines" externally??

SV> =====================

[Vishal Anand]

Hi,

It seems XL treats "`define ABC" and "`define ABC 1" differently. If
in a code you have

module abc ();

`define ABC

initial $fdisplay( `ABC, "ABC is defined");

endmodule

Then XL gives an illegal arguments error on the fdisplay system tasks.
If however you change the "`define ABC" to a "`define ABC 1" then not
only does the code work but the suggestion by Mike Hardy also works
fine.

All this makes me wonder if the statement "ifdef" is simply chacking if
the text macro has been define irrespective of what value it has
assigned (i.e. the value assigned could be 0)

[Shalom Bresticker]

Correct. And it's explicitly and clearly defined that way in the LRM.

Vishal Anand wrote:

> All this makes me wonder if the statement "ifdef" is simply chacking if
> the text macro has been define irrespective of what value it has
> assigned (i.e. the value assigned could be 0)

--

************************************************************************
Shalom Bresticker email: sha...@msil.sps.mot.com
Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522444
http://www.motorola-semi.co.il/
************************************************************************