Simple way to implement multi-stage pipeline design in Verilog

[carl.h...@gmail.com]

Hello, All,

I am trying to do some general tests by implementing
pipelined datapath on FPGA to see the timing behavior
of the signals on PADs, IOB FFs, DCM inputs and outputs,
BUFG, etc.

I think I will need to quickly generate a piece of design
that has many pipeline stages. The design does not
need to make sense but simply scalable to occupy
the FPGA chip.

Now, my question is: Is there a simple to way to compose
this type of RTL synthesizable code in Verilog with fewest
possible number of lines?

I do not want to use the "generate" feature since I am
not sure if the synthesis tool will accept it. Would a for loop
help to achieve this?

Thanks in advance for your help!

Carl Horton

[gabor]

If your synthesis has for loops, it probably has generate.

However you could do this without loops using arrays of
instances like (purely Verilog '95):

module shift_reg (d_out, d_in, clk);
parameter stages = 8;
input d_in, clk;
output d_out;
reg [stages-1:0] sreg;
always @ (posedge clk) sreg <= {sreg[stages-2:0],d_in};
assign d_out = sreg[stages-1];
endmodule

then instantiate like

shift_reg all_regs [128:0]
(
.d_in (all_inputs), // bus [127:0]
.d_out (all_outputs), // bus [127:0]
.clk (clock)
);