About use the Modelsim to simulate the FSM .

[hitajian]

As we know ,when we use the modelsim to simulate the FSM written in
VHDL,
we can see the state name in wave window . We can see IDLE,START......

But if the FSM written in Verilog , I can't see the state name .Just
only see the 0001,0010,......

How can I see the state name in the wave window ? It's just for debug
easily .

[Paul]

Add the following into your State logic ...
        casex (state)
          000:     state_name = "IDLE";
          001:     state_name = "STATE_1";
          010:     state_name = "STATE_2";
          011:     state_name = "STATE_3";
          default: state_name = 1'bx|"Bad state";

you can then use your favorite waves display program to watch the opcodes as they move through the pipe simply by displaying state_name and asking it to be displayed in ascii

- Paul

[Srinivasan Venkataramanan]

Hi,
Here is a solution posted some weeks back in this NG:

HTH,
Srini

`ifdef SIMULATION
parameter S_idle = "idle ";
parameter S_decode = "decode";
parameter S_start = "start ";
parameter S_wait = "wait ";
parameter state_wid_msb = 47;
`else
parameter S_idle = 4'b0001;
parameter S_decode = 4'b0010;
parameter S_start = 4'b0100;
parameter S_wait = 4'b1000;
parameter state_wid_msb = 3;
`endif

reg [state_wid_msb:0] state;

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India (http://www.vlsisrini.com)

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