Asynchronous FIFO - Different widths of Input & Output Ports.
Gokul
I require to use an Asynchronous FIFO, so as to allow a safe and
synchronised data transfer across two clock domains.One was the write
domain (clk_w) at which,the data (256 bit wide) is written into the
FIFO buffer (256 bit wide and 32 depth).The data nput port to the FIFO
is 256 bit wide.Other was the read domain (clk_r), at which the data
has to be read from the FIFO buffer. clk_w is 100 Mhz and clk_r is 800
MHz.
The data from the FIFO has to be read from and to be written into a
DRAM memory (32 bit wide and 1024 depth).Hence the data output port of
the FIFO from which data is transferred on to the DRAM is only 32 bit
wide.
How to achieve the read process (from the FIFO buffer) and write into
the DRAM memory utilizing the 32 bit output line of the FIFO
buffer.Suggest me a method to read through 32 bit line or to use a
circuit component in between FIFO & DRAM.
P.S: Fifo is a part of the Memory Controller.
Kevin Neilson
I've done something very similar in the design of a memory controller.
I made a FIFO from Xilinx BRAM, exploiting the asymmetric dataport
feature of the BRAMs. In this case, my FIFO would use eight BRAMs that
are 32x512 on the write side (this is the maximum width) to make the
256-wide port and 4x4096 on the read side to make the 32-wide port.
This requires modification of the Gray pointers, but it's fairly
straightforward. You just add a 3-bit counter (not Gray) to the Gray
counter on the read side so that there must be eight reads before the
Gray pointer advances, indicating to the write side that there is
another 256-bit slot open.
The problem you will have is that you won't be able to read at 800MHz in
an FPGA. You could possibly have two interleaved FIFOs which you could
read at 400MHz and use those to feed the DDR registers at 400MHz, if you
are trying to achieve a DRAM speed of DDR800. You might want to slow
down the DRAM rate. Often the throughput with DRAMs is not limited by
the max clock speed but by the memory controller wasting cycles between
bursts.
-Kevin