$sdf_annotate gives warnings for shorts in design

[SB]

All,

I have a problem with the annotation of an sdf
file to a netlist. The sdf is generated in Synopsys
PrimeTime and the $sdf_annotate task is called in
Synopsys VCS.

There are assign statements in the design. These
represent shorts that feed signals from the toplevel inputs,
through a sub-module, to another submodule at the same
level. This is to ease the layout task.
The shorts are represented in the sdf as:

(INTERCONNECT <start> <end> (0.000::0.000))

However, when the sdf_annotation encounters these shorts,
the following warning is caused:

Warning-[SDFCOM_SWC] Simple Wire Connection
<sdf file and line number of interconnect line above>
module: usb30dll_dll_top, "instance: <instance of the dut>"
SDF Warning: The path from <start> to <end> doesn't have a simple
wire connection, delay will still be annotated.

The sdf annotator is expecting to see the a simple continuous wire
but raises an warning when it sees the short.

Is there a way to prevent this warning from occurring either with the
sdf
generation step in Primetime or the SDF annotation step in VCS, or by
any other means?

Thanks
SB