Strings and ENV in verilog

[Michael Mortensen]

I am trying to do 2 things.

For one, if I have a `define for a filename (i.e. /a/b/c), is
there some way I can do string manipulation during the run so
that I can use the directory and a new file name (i.e. /a/b/new_file)?

Also, is there a way (aside from writing PLI) to get the value
of an environment variable (i.e. $PWD, or $MY_VARIABLE, etc.)?

I am trying to do this in a generic way, non-design specific way
so that the same code can work with any design via environment
variables and relative paths (for loading in things like vector files).

Thanks,
Mike

--
===========================================================
= Michael Mortensen =
= Motorola Unified Design Systems Lab =
= 5918 W. Courtyard Dr., Suite 330, Austin, TX 78730 =
= (512) 794-4340 mor...@udsl.sps.mot.com =
===========================================================

[Eric Williams]

Michael Mortensen <mor...@adttx.sps.mot.com> writes:
> For one, if I have a `define for a filename (i.e. /a/b/c), is there
> some way I can do string manipulation during the run so that I can
> use the directory and a new file name (i.e. /a/b/new_file)?

Strings can be manipulated as wide busses:

----- cut here ----------
`define FILENAME_MAX 1024
`define FILENAME_T `FILENAME_MAX*8:1
`define NAME "/a/b/c"

module test_bed;
initial begin
$display("filename: %0s", `NAME);
$display("dirname filename: %0s", dirname(`NAME));
$display("basename filename: %0s", basename(`NAME));
$display("new filename: %0s", {dirname(`NAME),"/new_file"});

$finish;
end // initial

function [`FILENAME_T] dirname;
input [`FILENAME_T] name;
begin
while (name[8:1] != "/") name = name >> 8;
name = name >> 8;
dirname = name;
end // function dirname;
endfunction // dirname

function [`FILENAME_T] basename;
input [`FILENAME_T] name;
begin
while (name[8:1] != "/") begin
basename = (basename << 8) | name[8:1];
name = name >> 8;
end // while
end // function basename;
endfunction // basename

endmodule // test_bed
----- cut here ----------

> Also, is there a way (aside from writing PLI) to get the value
> of an environment variable (i.e. $PWD, or $MY_VARIABLE, etc.)?

Not that I know of. Why not invest in some simple PLI? (Rather than
using environment variables, which are "hidden" in a users environment
and tend to lead to "but it works for me" situations, I tend to favor
general option parsing routines which allow you to pass in strings or
numbers via plusargs.)

-Eric

[Thomas A. Coonan]

>Not that I know of. Why not invest in some simple PLI? (Rather than
>using environment variables, which are "hidden" in a users environment
>and tend to lead to "but it works for me" situations, I tend to favor
>general option parsing routines which allow you to pass in strings or
>numbers via plusargs.)
>
>-Eric

That's interesting.. So, my even simpler question is how I use the
above to avoid this sort of tedious and repetitive thing:

# verilog <blah blah blah> +define+USE_SDF_BCCOMVERSIONXYZ
<blah> <blah> <blah>

`ifdef USE_SDF_BCCOMVERSIONXYZ
initial begin
$sdf_annotate ("amazing_product_bccom.verilogSDF",
top_amazing_inst);
end
`endif

As you can imagine, I end up with a dozen stupid blocks for every
delay case and netlist I might want to handle. Works, but would
rather pass filename from command line.

tco...@mindspring.com
http://www.mindspring.com/~tcoonan

[Edward S. Arthur]

Michael Mortensen <mor...@adttx.sps.mot.com> wrote in article
<33732BEE...@adttx.sps.mot.com>...

> I am trying to do 2 things.
>

> For one, if I have a `define for a filename (i.e. /a/b/c), is
> there some way I can do string manipulation during the run so
> that I can use the directory and a new file name (i.e. /a/b/new_file)?

String manipulation is very difficult in Verilog - I wouldn't
want to attempt it.

> Also, is there a way (aside from writing PLI) to get the value
> of an environment variable (i.e. $PWD, or $MY_VARIABLE, etc.)?
>

> I am trying to do this in a generic way, non-design specific way
> so that the same code can work with any design via environment
> variables and relative paths (for loading in things like vector files).

There are plenty of PLI routines available to put a plus_arg into a
string variable; appending strings inside Verilog is easy though:
(str = {str1, str2};)

/Ed

[Eric Williams]

Thomas A. Coonan <tco...@mindspring.com> writes:
> That's interesting.. So, my even simpler question is how I use the
> above to avoid this sort of tedious and repetitive thing:
>
> # verilog <blah blah blah> +define+USE_SDF_BCCOMVERSIONXYZ
> <blah> <blah> <blah>

verilog <blah blah blah> +sdf_filename=amazing_product_bccom.verilogSDF

initial begin
// $getstr$plusarg is a PLI function that returns a string argument
// of the form "+plusarg=string" into a verilog variable.
if ($getstr$plusarg("sdf_filename=", filename) == 1) begin
// plus arg was used, filename has the arg
$sdf_annotate(filename, top_amazing_inst);
end

The catch is that you still can't pass in arguments that would allow
you to select different instances but if your hierarchy is constant
enough that you can leave it constant then this is the method for you.

-Eric

[Janick Bergeron]

In article <33746a5a...@news.mindspring.com>,

Thomas A. Coonan <tco...@mindspring.com> wrote:
>That's interesting.. So, my even simpler question is how I use the
>above to avoid this sort of tedious and repetitive thing:
>
># verilog <blah blah blah> +define+USE_SDF_BCCOMVERSIONXYZ
> <blah> <blah> <blah>
>

>`ifdef USE_SDF_BCCOMVERSIONXYZ
>initial begin
> $sdf_annotate ("amazing_product_bccom.verilogSDF",
>top_amazing_inst);
>end
>`endif
>
>As you can imagine, I end up with a dozen stupid blocks for every
>delay case and netlist I might want to handle. Works, but would
>rather pass filename from command line.

What about wrapping Verilog in a PERL script that will generate
a module containing the necessary statements on-the-fly and
include this new module in the simulation?

E.g. from you example above:

module SDF_ANNOTATE;

initial begin
$sdf_annotate ("amazing_product_bccom.verilogSDF",
top_amazing_inst);
end

endmodule

Then call verilog as follow:

% verilog <blah blah blah> <blah> <blah> <blah> /tmp/sdf_annotate.v

The module containing the $sdf_annotate call need not be instantiated
anywhere and can be an alternative root module.

In large simulation management problems, wrapping verilog in PERL
to manage testcases, DUT configuration, logging, delay case,
and other house keeping chores is a common practice.

--
Janick Bergeron Qualis Design Corporation Ph.: (503) 350-3663
Director of PO Box 4444 Fax: (503) 643-1583
Technology Beaverton, OR, USA, 97075-4444 jan...@qualis.com
VHDL - Verilog - Synthesis - Modelling - Verification - Training

[Chris Spear]

Eric Williams wrote:

> initial begin
> // $getstr$plusarg is a PLI function that returns a string argument
> // of the form "+plusarg=string" into a verilog variable.
> if ($getstr$plusarg("sdf_filename=", filename) == 1) begin
> // plus arg was used, filename has the arg
> $sdf_annotate(filename, top_amazing_inst);
> end
>

$getstr$plusarg is not an IEEE standard task and is not available
in most simulators.

--
--------------------------------------------------------------------
Chris Spear Field Applications Engineer
Viewlogic Systems, Inc. Email: sp...@viewlogic.com .. __o
293 Boston Post Road Phone: (508) 303-5252 _`\<,_
Marlboro, MA 01752-4615 Fax: (508) 480-0165 .. (*)/ (*)
--------------------------------------------------------------------