Thanks for all your reply.I got the combinatorial PAL16L8 design working, the trick was to use the 'wire' variable since there is feedback of one output (pin 19).i aso applied some delay to outputs.This is the working code tested onto a small CPLD :
default_nettype none
`timescale 1 ns / 100 ps
module PAL16L8_U8(
input i1, i2, i3, i5, i6, i7, i8, i9, i11,
output o12, o13, o14, o15, o16, o17, o18, o19);
wire R19;
assign #7 o12 = ~(i3 & i5 & i6 & ~i7 & i9);
assign #7 o13 = ~(i3 & i5 & ~i6 & ~i7 & i8 & i9);
assign #7 o14 = ~(i3 & ~i5 & i6 & ~i7 & i9);
assign #7 o15 = ~(i3 & ~i5 & ~i6 & ~i7 & i9);
assign #7 o16 = ~((~R19) |
(i3 & R19 & ~i5 & i6 & ~i7 & i9) |
(i3 & R19 & i5 & i6 & ~i7 & i8 & i9));
assign #7 o17 = ~((R19 & ~i5 & ~i8) |
(i3 & R19 & ~i5 & i6 & ~i7 & i8 & i9) |
(i3 & R19 & ~i5 & ~i6 & i7 & i8 & i9));
assign #7 o18 = ~((i3 & R19 & ~i5 & ~i6 & i9) |
(i3 & R19 & i5 & ~i6 & ~i7 & i8 & i9) |
(i3 & R19 & ~i5 & i6 & ~i7 & i8 & i9));
assign #7 R19 = ~(i3 & ~i5 & ~i6 & ~i7 & i8 & i9 & i11);
assign #7 o19 = R19;
endmodule
The registered design is still noy working although also here I modified it using 'wire' and 'reg' variables.Here is code :
module pal16r4_u14
(input wire clk, i2, i3, i4, i5, i6, i7, i8, i9,
output wire o12, o13, o18, o19,
output reg reg_o14, reg_o15, reg_o16, reg_o17);
assign o12 = ~R13;
wire R13;
assign R13 = ~((reg_o17 & R18) |
(o16 & ~R18 & ~R19));
assign o13 = R13;
wire o14;
always @(posedge clk)
begin
reg_o14 <= o14;
end
assign o14 = ~((~i2)
| (i2 & ~i4 & reg_o14)
| (i2 & i4 & ~reg_o14));
wire o15;
always @(posedge clk)
begin
reg_o15 <= o15;
end
assign o15 = ~((~i2)
| (i2 & ~i4 & ~i5 & ~reg_o14 & reg_o15)
| (i2 & ~i4 & i5 & reg_o14 & reg_o15)
| (i2 & i4 & ~i5 & reg_o14 & reg_o15)
| (i2 & i4 & ~reg_o14 & ~reg_o15)
| (i2 & i5 & ~reg_o14 & ~reg_o15)
| (i2 & ~i4 & ~i5 & reg_o14 & ~reg_o15)
| (i2 & i4 & i5 & reg_o14 & ~reg_o15));
wire o16;
always @(posedge clk)
begin
reg_o16 <= o16;
end
assign o16 = ~((~i2)
| (i2 & ~i5 & reg_o15 & reg_o16)
| (i2 & ~i4 & ~i5 & reg_o14 & reg_o16)
| (i2 & i5 & ~reg_o16)
| (i2 & i4 & ~reg_o15 & ~reg_o16)
| (i2 & ~reg_o14 & ~reg_o15 & ~reg_o16));
wire o17;
always @(posedge clk)
begin
reg_o17 <= o17;
end
assign o17 = ~((~i2)
| (i2 & ~i3 & i6 & reg_o17)
| (i2 & ~i3 & reg_o17)
| (i2 & ~i5 & i6 & reg_o17 & ~R19)
| (i2 & i3 & i5 & ~reg_o17)
| (i2 & i3 & ~i6 & ~reg_o17)
| (i2 & i3 & ~reg_o17 & R19)
| (i2 & ~i6 & ~reg_o17 & R19));
wire R18;
assign R18 = ~((i3 & reg_o17) |
(~i3 & ~reg_o17 & R19));
assign o18 = R18;
wire R19;
assign R19 = ~((~i4 & reg_o15 & reg_o16)
| (~i4 & reg_o14 & reg_o16));
assign o19 = R19;
endmodule