Modeling Bus Repeaters

[Tim Sterczyk]

Hi,

I have a design which contains many tri-state busses and uses bus-
repeater cells (or bus-holders) to maintain the value on a bus even
when it is not driven. The Verilog model for the bus repeater in our
ASIC vendor's cell library looks something like this:

module bus_repeater (z);

inout z;
trireg (medium) z;

endmodule

When no other drivers on the bus are active, the bus repeater "drives"
the bus with a medium capacitance strength. Functionally, this model
works fine. However, some PLI routines which I'm using consider a
signal driven by a capacitance strength to be an error.

Therefore, I've been trying to remodel the bus repeater cell so that
it drives with a weak drive or pull drive, but I haven't been able to
get anything to work. For example, writing something like this causes
signal "z" to become unknown:

module bus_repeater_wrong (z);

inout z;
trireg (medium) z;

buf (z,z);

endmodule

Any suggestions on how such a bus-repeater could be modelled? Thanks
in advance.

---

Tim Sterczyk
PMC-Sierra Inc.
8501 Commerce Court
Burnaby, BC V5A 4N3
e-mail: ster...@pmc-sierra.bc.ca