2 non-blocking assignments at same time -- who wins?
VhdlCohen
always @(posedge clk)
begin
a_1st <= 1'b0;
if (c == 1'b1)
a_1st <= 1'b1;
end
and c = 1, then this would be equivalent to
a_1st <= 1'b0;
a_1st <= 1'b1;
Who wins? In VHDL, last assignment wins. In Verilog, this would produce TWO
non-blocking events. When all regular events are processed, these 2
non-blocking events are retrieved IN ANY ORDER, and converted to regular
events. RIGHT?
The reason I think this is correct is because in all books I have seen, there
is no mention of inertial delay. Also in FSMs, the style of using a default
for the FSM state reg is never used in Verilog. Thus, the foollowing is
discouraged:
nextstate <= currentstate;
if currentstate == IDLE // IDLE is a constant
nextstate <= GODO;
Instead, all books and synthesis venndors want you to do this:
if currentstate == IDLE // IDLE is a constant
nextstate <= GODO;
else
nextstate <= IDLE;
In addition, from Thomas and Moorby book "The Verilog HDL, 4th ed." page 178,
the algorithm for handling timing is as follows:
Non-blocking events are put on the non-blocking event list
regular (e.g., procedural) events are put on the regular event list.
Monitor events are put on a monitor event list.
Now, While there are regular events:
“retrieve all regular events for current time and execute in arbitratry order”
Note: These may produce more regular events for current time
When that is done, Retrieve all non-blocking events for the current time and
make them regular events. Now execute.
These may produce more regular events for current time, if so
When no more events, do monitor events. No new events produced.
Comments on this are appreciated.
Please mail it your comments to vhdl...@aol.com
Thanks,
Ben Cohen
Eric Decker
always @(c)
begin
a_next = 1'b0;
if (c == 1'b1)
a_next = 1'b1;
end
always @(posedge clk)
begin
a_1st <= a_next;
end
Why? I think that it is much easier to keep track of, and does not require a
roomful of the verilog masters to decipher the standard -- which simulator vendors
are not guaranteed to implement correctly. This is also guaranteed to synthesize
accurately. As you pointed out, this is recommended in texts and by tool vendors.
Eric Decker
Hagen Sankowski
>
> If I have the following:
> always @(posedge clk)
> begin
> a_1st <= 1'b0;
> if (c == 1'b1)
> a_1st <= 1'b1;
> end
I know that coding style in VHDL quite well, but in Verilog it's a big
trap. Sometimes it will work.
IMHO you should resolve such 'default' coding style with *else* branches.
This works fine both in simulation *and* synthesis.
Regards,
hsank.
Jan Decaluwe
>
> VhdlCohen wrote:
> >
> > If I have the following:
> > always @(posedge clk)
> > begin
> > a_1st <= 1'b0;
> > if (c == 1'b1)
> > a_1st <= 1'b1;
> > end
>
> I know that coding style in VHDL quite well, but in Verilog it's a big
> trap. Sometimes it will work.
> IMHO you should resolve such 'default' coding style with *else* branches.
In this case, that would be almost equivalent, but in many other
more practical cases not. For example, suppose you want to
turn on a flag only under a very specific condition in a
conditional hierarchy. Using a default is very elegant
and results in short code. Resolving the "else" conditions
manually may be painful and error-prone.
Take another common example of an FSM with many output. Typically,
many outputs will have some default value in most states. Instead
of listing all outputs in all states, it's much more elegant
and shorter to deal with the default case first. I know that
many hardware designers don't do this, but I insist it's
good coding practice to deal with the general case first
and handle the specific cases separately.
> This works fine both in simulation *and* synthesis.
When I first designed with Verilog, non-blocking assignments
didn't even exist - yet we also designed chips with it.
Non-blocking assignments VHDL-style would have been a good
addition - but that's not what we got. The resulting ongoing
confusion about how non-blocking assignments in Verilog
actually work is just horrible.
Jan
--
Jan Decaluwe Easics
Design Manager System-on-Chip design services
+32-16-395 600 Interleuvenlaan 86, B-3001 Leuven, Belgium
mailto:ja...@easics.be http://www.easics.com
taniwha
>
> If I have the following:
> always @(posedge clk)
> begin
> a_1st <= 1'b0;
> if (c == 1'b1)
> a_1st <= 1'b1;
> end
>
> a_1st <= 1'b0;
> a_1st <= 1'b1;
> Who wins? In VHDL, last assignment wins. In Verilog, this would produce TWO
> non-blocking events. When all regular events are processed, these 2
> non-blocking events are retrieved IN ANY ORDER, and converted to regular
> events. RIGHT?
No - the LRM (2.0 at least) goes out of its way to ensure that consequtive
non-blocking assigns (special case here!) from the same sequential block
will result in consequtive assignments - in the same order. If it doesn't it's
a bug.
Of course if you try and detect the 2 events with something like
always @(a_1st) ....
you may or may not get triggered twice
Paul
igla...@my-deja.com
>> Also in FSMs, the style of using a default for the FSM state reg is
never used in Verilog
this is also not exactly correct, and here a small example :
always @ (sm, ...
begin
sm_d = sm ; // <---- This is the defualt meaning stay in same state
casex (sm)
...
endcase
end
always @ (posedge clk or negedfe reset_n)
if (~reset_n)
sm <= #1 0 ;
else
sm <= #1 sm_d ;
have a nice day
Illan
In article <3922A346...@taniwha.com>,
Sent via Deja.com http://www.deja.com/
Before you buy.
Utku Ozcan
> Take another common example of an FSM with many output. Typically,
> many outputs will have some default value in most states. Instead
> of listing all outputs in all states, it's much more elegant
> and shorter to deal with the default case first. I know that
> many hardware designers don't do this, but I insist it's
> good coding practice to deal with the general case first
> and handle the specific cases separately.
I think this technique has been covered in many VHDL/Verilog
books, and in two-always (two-process in VHDL) examples.
> > This works fine both in simulation *and* synthesis.
>
> When I first designed with Verilog, non-blocking assignments
> didn't even exist - yet we also designed chips with it.
> Non-blocking assignments VHDL-style would have been a good
> addition - but that's not what we got. The resulting ongoing
> confusion about how non-blocking assignments in Verilog
> actually work is just horrible.
=:c))
Utku
--
I feel better than James Brown.
Luan, Hao [WDLN2:2W43:EXCH]
I believe a SNUG paper (from www.synopsys.com) :"Nonblocking Assignments in
Verilog Synthesis, Coding Styles that kill" written by Clifford E. Cummings from
Sunburst Design Inc will answer your question perfectly. In this paper, you will
see a lot more coding style suggestions you need for a good design .
Regards
Hao Luan
******* This email only represents the ideas of myself not the organization I am
with *************
Thomas C. Jones
VhdlCohen
Ben Cohen