Constraint in SystemVerilog

[Amir]

Hi,
I would like to write a constraint in SystemVerilog which is like:

for(int i=0;i<`DATA_TRANS;i++)
begin
constraint c_prk_data_rdy_delay {
prk_data_rdy_delay[i] inside {[lo_delay:hi_delay]};
}
end

but it's not working, do you have any idea how can I enter a variable
in an constraint such as the aforementioned example?

Thanks a lot
-Amir

[Jonathan Bromley]

I guess you want a constraint on every element of
the array? That's straightforward, using an array
constraint:

constraint all_delays_sensible {
foreach (prk_data_rdy_delay[i]) {

prk_data_rdy_delay[i] inside {[lo_delay:hi_delay]};

};
}

You can also use the subscript [i] in the constraint.
So, for example, suppose you also wanted all even-numbered
elements of the array to be zero, and the highest-
numbered element of the array to be an odd number:

constraint all_delays_silly {
foreach (prk_data_rdy_delay[i]) {
if (i%2 == 0)
// Even-numbered subscript: constrain to zero
prk_data_rdy_delay[i] == 0;
else
// Odd-numbered subscript: constrain into range

prk_data_rdy_delay[i] inside {[lo_delay:hi_delay]};

// Additional constraint on highest-numbered element:
i == $high(prk_data_rdy_delay) ->
prk_data_rdy_delay[i] % 1 == 1;
}

Hope this helps
--
Jonathan Bromley, Consultant

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[Amir]

thanks :) it's working