What does "&&&" mean?
Tim Sterczyk
I've been going through some of the Verilog manuals and came across an
example which used a "&&&" operator. The example was a setup and hold
check between the clock and data signal of a D flip flop. Specifically,
the Verilog statement is:
$setuphold(posedge clk &&& rst, d &&& rst, 3:5:6, 2:3:6);
I would guess that this statement causes the setup and hold check to be
performed only when "rst" (reset) is high. Is this right? Does anyone
know just exactly what the "&&&" operator does and what it is called? I
cannot seem to find a description in any of the manuals. Thanks in
advance.
--
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| Tim Sterczyk | I am the dumbest man on the planet! |
| ster...@bnr.ca | - courtesy of David Letterman |
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Craig Botkin
: Hi,
Tim,
Chapter 13 of the Cadence Verilog manuals explain this in the discussion of
timing checks (13-59).
Basically the above statement only does the setup and hold check when the rst
is high. Also note that
$setuphold(posedge clk &&& (rst==0), d &&& (rst==0), 3:5:6, 2:3:6);
will cause the timing check to be performed when the reset is a 0 or an x
(underministic) whereas
$setuphold(posedge clk &&& (rst===0), d &&& (rst===0), 3:5:6, 2:3:6);
causes the timing check to be performed only when the reset is 0.
--
Craig Botkin
Interphase Corporation
bot...@iphase.com