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verilog and runtime directive around continuous assignment
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sense
Dec 8, 2011, 5:08:40 PM12/8/11
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Hi all,
I have a continuous assingment in verilog which I want to exclude in a
simulation under certain condition. Having a `ifdef `endif around the
code requires me to recompile and I cannot have a testplusarg around a
continuous assignment.
Any way to work around this problem?
Sagar
I have a continuous assingment in verilog which I want to exclude in a
simulation under certain condition. Having a `ifdef `endif around the
code requires me to recompile and I cannot have a testplusarg around a
continuous assignment.
Any way to work around this problem?
Sagar
glen herrmannsfeldt
Dec 8, 2011, 5:36:45 PM12/8/11
to
sense <sagar...@gmail.com> wrote:
> I have a continuous assingment in verilog which I want to exclude in a
> simulation under certain condition. Having a `ifdef `endif around the
> code requires me to recompile and I cannot have a testplusarg around a
> continuous assignment.
What do you want it to be when it isn't assigned?
> I have a continuous assingment in verilog which I want to exclude in a
> simulation under certain condition. Having a `ifdef `endif around the
> code requires me to recompile and I cannot have a testplusarg around a
> continuous assignment.
> Any way to work around this problem?
assign x = (condition) ? value : 8'hz;
That is, tristate based on condition. Though zero might
be a better choice.
-- glen
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