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Feb 28, 2023, 10:49:29 AMFeb 28

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I am writing verilog code & testbench to convert from octal number to binary number but I am not getting correct output. Here is the code & testbench let me know where I am making mistakes.

Code:

module octal_to_binary(

input [11:0] octal,

output reg [35:0] binary

);

integer i, j;

reg [2:0] octal_digit;

always @(*) begin

binary = 0;

for (i = 0; i < 4; i = i + 1) begin

octal_digit = octal[i*3 +: 3];

for (j = 0; j < 3; j = j + 1) begin

binary[i*9 + j*3 +: 3] = octal_digit[j];

end

end

end

endmodule

Tesrbench:

`include "octtobin.v" // adding design file

module tb;

reg [11:0] octal;

wire [35:0] binary;

integer i;

octal_to_binary dut (.*);

initial begin

//for (i = 0; i < 256; i= i+1) begin

octal = 4'o1234;

#30;

$display("Octal: %o Binary: %d", octal, binary);

//end

end

initial begin

$dumpfile("test.vcd");

$dumpvars(0,tb);

end

endmodule

Code:

module octal_to_binary(

input [11:0] octal,

output reg [35:0] binary

);

integer i, j;

reg [2:0] octal_digit;

always @(*) begin

binary = 0;

for (i = 0; i < 4; i = i + 1) begin

octal_digit = octal[i*3 +: 3];

for (j = 0; j < 3; j = j + 1) begin

binary[i*9 + j*3 +: 3] = octal_digit[j];

end

end

end

endmodule

Tesrbench:

`include "octtobin.v" // adding design file

module tb;

reg [11:0] octal;

wire [35:0] binary;

integer i;

octal_to_binary dut (.*);

initial begin

//for (i = 0; i < 256; i= i+1) begin

octal = 4'o1234;

#30;

$display("Octal: %o Binary: %d", octal, binary);

//end

end

initial begin

$dumpfile("test.vcd");

$dumpvars(0,tb);

end

endmodule

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