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checking if a register is undefined
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rekz
24 mar 2010, 13:02:5524.03.2010
do
Is there a way to check if the value of a register in verilog is
undefined? If there is then how?
undefined? If there is then how?
Muzaffer Kal
24 mar 2010, 13:05:5324.03.2010
do
On Wed, 24 Mar 2010 10:02:55 -0700 (PDT), rekz <adity...@gmail.com>
wrote:
wrote:
>Is there a way to check if the value of a register in verilog is
>undefined? If there is then how?
Yes; "if (fooreg === X)"
--
Muzaffer Kal
DSPIA INC.
ASIC/FPGA Design Services
Dave Rich
24 mar 2010, 13:15:0124.03.2010
do
On Mar 24, 10:02 am, rekz <aditya15...@gmail.com> wrote:
> Is there a way to check if the value of a register in verilog is
> undefined? If there is then how?
> Is there a way to check if the value of a register in verilog is
> undefined? If there is then how?
In Verilog, use the exclusive xor reduction operator to produce a
single bit. If the result is 1'bx, at least one bit of the register
was X
if (^myreg === 1'bx) ...
In SystemVerilog, you can use
if ($isunkown(myreg)) ...
johnp
25 mar 2010, 12:01:0925.03.2010
do
On Mar 24, 10:02 am, rekz <aditya15...@gmail.com> wrote:
> Is there a way to check if the value of a register in verilog is
> undefined? If there is then how?
> undefined? If there is then how?
If you mean in simulation, then yes, you can check for X, see other
replies. If you mean in actual h/w, ie, synthesized design, then the
answer is no.
John Providenza
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