What's the difference between "XOR" and "^" ?

[Tom Huang]

Hello

I thank that "XOR" is the same with "^" in Verilog.
For example, I get the same result in Verilog simulator,
for using "xor (temp,A[0],B[3]);" and " assign temp=A([0]^B[3]);".

But they seem not to get the same result in Synopsys Design Analyzer.
If I use "^", I can see a XOR gate in schematic view. However, if I
use "XOR", I can't see the XOR gate in schematic view. XOR becomes a
"block"(I guess this "block" is a library element, but I am not
sure.).

I am a beginner in synthesis. Please tell me why "XOR" and "^" are
different in Synopsys Design Analyzer. Which one is the better choice
for synthesis?

[Kant Kong]

We recommend to use "^" in design, when Design Compiler read your code, it
map all logic to libaray cell, so it find matching "XOR" cell for operator
"^", like "XOR2X1", "XOR2X2"... But for Verilog Primitive "XOR", DC treat
it as special cell, don't map it. So when you Design Analyzer view, DA find
the symbol of "XOR2X1" in ASIC library or Synopsys's GTECH library, but DA
don't find any symbol for "XOR", so you only see a "block" for it.

ke...@tehlu.es.ncku.edu.tw (Tom Huang) wrote in
<ec555866.01081...@posting.google.com>: