how do you add bidirectional delay?
Peter Young
simple (and common) thing, but searching the web and usenet archives on
Google didn't turn up an answer on how to do it.
I am setting up a test environment for a SDRAM controller, and I want
to model the delay on the bidirectional data bus between my FPGA and the
memory chip.
- Since it's bidirectional, I can't do a simple delay assignment.
- I tried creating a module using a specify block (shown below), since
my Verilog book said specify delays would work with inout ports, but
instantiating that in the data path didn't work either.
- I'd prefer to avoid hacking the vendor memory model to add my trace
delays there.
Does anyone know of a simple way in Verilog to add a delay without
adding the delay to the seperate in, out, and tristate components of the
signal source?
Thanks,
Pete
(if you reply by e-mail, please remove the spam block in the address)
--
Peter Young
Hardware Designer
AMIRIX Systems - Halifax, N.S.
http://www.amirix.com
Peter Young
include it in the original message).
module bidirdelay (a, b);
/*************
* Parameters *
*************/
parameter sig_width = 1;
/*************
* Module I/O *
*************/
inout [sig_width-1:0] a;
inout [sig_width-1:0] b;
/****************
* Specify Block *
****************/
specify
specparam ab_delay = 0.527;
( a => b ) = ab_delay;
( b => a ) = ab_delay;
endspecify
endmodule
Nahum Barnea
> Here was the delay module I attempted using a specify block (forgot to
> include it in the original message).
>
>
> module bidirdelay (a, b);
>
> /*************
> * Parameters *
> *************/
> parameter sig_width = 1;
>
> /*************
> * Module I/O *
> *************/
> inout [sig_width-1:0] a;
> inout [sig_width-1:0] b;
>
> /****************
> * Specify Block *
> ****************/
> specify
>
> specparam ab_delay = 0.527;
>
> ( a => b ) = ab_delay;
> ( b => a ) = ab_delay;
>
> endspecify
>
> endmodule
One solution can be usingverilog "tran" .
Steven Sharp
> Peter Young <Peter...@SPAMBLOCKHERE.amirix.com> wrote in message news:<3D47FEC5...@SPAMBLOCKHERE.amirix.com>...
>
A tran switch cannot provide a bidirectional delay. The delay on
the primitive is just a delay on changes to the control input
taking effect.
The implementation of a bidirectional delay is far more complex
than it might appear. There are reasons why it isn't readily
available in the language.
You might be able to get the desired effect by back-annotating
interconnect delays from all of the drivers to all of the readers,
such that any path that goes through your desired bidirectional
delay has an increased delay. I am not sure it would work, and
it would take a lot of effort.
Steve Meyer
(see any LRM). All drivers of inout channel (sources) are "shorted" to
all loads (sinks). But Verilog does support placing delays after all
drivers of inout channel (sources) so that new driving value of source is not
seen by inout channel (used in strength comopetition) until after delay
(path and gate delays are used for this). Strength competition includes
all drivers on any wire connected by an inout port (maybe throughout
all of instance hierarchy) that is not tristated or tranif that is
turned on.
Also, delays can be placed before inout channel loads (sinks - values that
use inout channel value as input) so that newly calculated inout tran
channel strength value does not change input until delay elapses. These
are called MIPDs (module input port delays). Delay calculators and SDF
files handle this. Unfortunately, the only way to set a MIPD requires
either using SDF or PLI delay annotation.
I do not think there is reasonable digital alternative for the
Verilog semantics. Or am I wrong?
/Steve
--
Steve Meyer Phone: (612) 371-2023
Pragmatic C Software Corp. email: sjm...@pragmatic-c.com
520 Marquette Ave. So., Suite 900
Minneapolis, MN 55402