Verilog based PCB design flow?
Petter Gustad
Are there any PCB design packages which let you do your PCB layout
using a Verilog netlist as source?
In most PCB CAD programs you'll have to draw a schematics and draw
symbols for each part. I would like to use a Verilog (or even EDIF)
netlist as a base for the PCB layout work. Of course the physical
parameters for each part has to be specified and mapped to their
respective instances in the verilog netlist.
Petter
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Spam Hater
Verilog netlist? Do you mean a netlist created from a Verilog
structural representation? If so, OrCAD can do that.
On 20 Jul 2003 12:31:19 +0200, Petter Gustad
Petter Gustad
> Verilog netlist? Do you mean a netlist created from a Verilog
> structural representation? If so, OrCAD can do that.
I mean a Verilog netlist I write in a text editor which instantiate
components used on the PCB. I would be happy if somebody could point
me to some documentation (URL's) on how to do this in OrCAD.
Spam Hater
Step 1) Create netlist from Verilog source.
Step 2) Read netlist into PCB editor.
I think you're missing step 1. Verilog is not a netlist; netlists are
created from Verilog.
On 21 Jul 2003 01:19:54 +0200, Petter Gustad
Andy Peters
> Spam Hater <spam_h...@email.com> writes:
>
> > Verilog netlist? Do you mean a netlist created from a Verilog
> > structural representation? If so, OrCAD can do that.
>
> I mean a Verilog netlist I write in a text editor which instantiate
> components used on the PCB. I would be happy if somebody could point
> me to some documentation (URL's) on how to do this in OrCAD.
What you need is a tool that "synthesizes" the Verilog and outputs a
netlist in perhaps Tango (or whatever) format that the PCB layout tool
can import. The tool would have to understand your PCB layout
software's library structure.
I know of a text-based design-entry tool flow but it's based on a
proprietary language. I haven't seen one that uses Verilog or VHDL.
If you were to use Verilog or VHDL for this sort of thing, I think
you'd have to use a subset of the language. For instance, a schematic
doesn't understand anything about timing. Basically, you'd use the
HDL to instantiate blocks and wire them together.
But that's actually OK. Consider that the HDL simulator could pull
real models from a library so you could simulate your whole board.
The PCB netlister tool would simply pull a footprint from the library.
And imagine using generates to instantiate a whole bunch of memory
chips, rather than having to place each one on the schematic and wire
them up.
Also, using an HDL would let you do some very useful things that are
difficult and cumbersome to do from a schematic. For example, say you
have a design that can accept different sized (as in capacity, not
footprint!) memory devices. You can use generates and parameters to
create stuffing guides with the different parts as needed.
I guess the final advantage is that the design entry is text based.
Source-control programs work without problems. Searching files for
instances of whatever is a piece of cake. And there's no worries
about your schematic tools vendor changing the format, or going out of
business!
---a
Greg
your netlist and import into a layout tool; afterall, a schematic
basically creates this file upon exporting logic, but there is more to
it than that, believe me, I know from personal experience! A schematic
tool creates other files also. So, basically to import a third party
netlist into Cadence Allegro, for example, it requires a text netlist
that is formatted a specific way and a bunch of device files or text
files for each device type in your design. It is possible to manually
do this without a schematic tool, per se, but I would not recommend
it. Unless, of course, your design is really, really
non-complex...there is too much room for error in creating this stuff
yourself through text files. It is really, really easy to create
schematic symbols in Cadence Concept. Doing the schematic takes time
and time to do the physical symbols.
Although, If you already have a EDIF netlist, I am not sure if you can
import that into a schematic tool and create a actual schematic??? I
take it that your synthesis tool create this EDIF netlist?
Petter Gustad <newsma...@gustad.com> wrote in message news:<874r1hl...@zener.home.gustad.com>...