It's Actually Verilog this time...

[Rick C]

Gowin Synthesis User Guide SUG550

semi-dual-port B-SRAM

module read_first_wp_pre_1(data_out, data_in, waddr, raddr,clk,
rst,ce, wre);
output [10:0]data_out;
input [10:0]data_in;
input [6:0]raddr,waddr;
input clk, rst,ce, wre;
reg [10:0] mem [127:0];
reg [10:0] data_out;

always@(posedge clk)
if(ce |wre)
data_out <= mem[raddr];

always @(posedge clk)
if (rst)
mem[waddr] <= data_in;
else if (ce | !wre) mem[waddr] <= data_in;

endmodule


Correct me if I'm wrong, but isn't if(ce |wre) going to OR the clock enable and the write enable? Anyone seen a BRAM work that way?

Also, anyone think anything is odd about an async reset signal on a sync BRAM? It's not even a reset of the whole memory, just the addressed location. Even odder is the circuit diagram they show runs the rst signal to the output register only. Heck, the output register is optional.

https://www.gowinsemi.com/upload/database_doc/1232/document/5f7befe0a7c86.pdf

B-SRAM & S-SRAM User Guide

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Rick C.

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[Kevin Neilson]

This is code from the manual? It's not great. First of all, they're using the double-declared port style that was deprecated by Verilog-2001. Also, there are no comments.

The reset shown is not asynchronous (only the clk is in the sensitivity list). However, the reset behavior in the code is still weird. Normally, a RAM reset would only affect the output register, like you say the circuit diagram indicates. And why would the RAM be written when ce=0, wre=0 (in which case (ce | !wre)=1 )? I don't think this code is behaviorally accurate.