//// my module
module modmod( input wire a,
output wire b);
parameter some_param;
.
.
.
endmodule
// it's instances:
modmod my_ins[4:0](.a(a), .b(b));
// I'm passing the params like this:
defparam my_ins[0].some_param = 3;
etc.
thanks in advance, GilGr
from the LRM:
An individual instance from an array of instances shall be
referenced in the same manner as referencing an element of
an array of regs.
For example:
The following declaration of nand_array declares four instances
that can be referenced by nand_array[1], nand_array[2],
nand_array[3], and nand_array[4], respectively.
nand #2 nand_array[1:4]( ... ) ;
Your syntax seems to follow the LRM. Arrays of instances was
a relatively new feature of Verilog 95, and some synthesis tools
didn't handle them at all, so I wouldn't be surprised if others
don't handle the naming of instances correctly. If you have
a way to look at nets in the translated EDIF or other output
of the synthesis, perhaps you can figure out the naming convention
used by synopsis DC and try to match that in your defparam.
Regards,
Gabor
Alex
Of course that method would apply the same parameter value to all
instances. Not as generally applicable as defparam. However if
that does the trick, use it. My guess is that it won't do the
trick or the parameter defaults would have been set as desired
in the module where they were defined.