You can use it quite freely, I only ask that you keep my copyright
header notice intact, even if you change the module name, or merge
it into your verilog code, or even if you translate it to VHDL
(shouldn't be hard). It's coded as a combinational block, so you
would add your own flop external to each block to latch disparity.
Logic designers might find a few other interesting things at my site,
and I hope to continue to add useful stuff - please feel free to offer
any feedback.
\chuck
Chuck Benz
ASIC and FPGA design
news...@chuckbenz.com