Using strings data types to force/probe desing signals (wires)

[djarte]

Hi everybody,

I am writing a generic verification task so i would like to parse the information of a table including signal names for a specific digital RTL block. I thought it could be a good idea to use a string data type to hold the signal names and then try to force them or probe them within my verification task. The problem is that as far as i know system verilog does not support string data types in force/probe commands. Please see the example below:

typedef struct { byte chicken_bit;
byte num_blocks;
string blk_names[];
string blk_clk[];
string blk_en_clk_check[];
string blk_clk_req[];
int clk_freq[];
} chicken_bit_s;

chicken_bit_s chicken_bit_table[];

There is a struct holding row information from the table initialized before compilation time. Also the dynamic array chicken_bit_table contains on each index the information for a specific struct variable (row). The dynamic string arrays defined inside the struct are used because each struct copy variable can have different number of strings. For example the blk_clk [] string dynamic array is initialized to the values {"tmp1_clk", "tmp2_clk"} where tmp1_clk and tmp2_clk are actual clk wires defined in the RTL. Ideally i would like to use this string array elements to force or probe this signals in the RTL. As i said before this is not allowed in system verilog. You cannot probe or force a string. I can't also define this array as dynamic wire array and then initialize it using define commands to the hierarchy path of the actual wires.

Any suggestion to solve this issue would be really valuable for me.

Thanks in advance.

[Mark Curry]

In article <09546fe4-1947-46f6...@googlegroups.com>,

I've done similar in the past (well, just the probing part), and it boiled down to
one of two solutions:
1. Leverage the PLI
2. Using a Modelsim hook into TCL.

I chose the latter. Basically, I created some TCL in modelsim which monitored
for changes on an wire. When changes occured, it indicated that the testbench
wished to change what was being probed. From there modelsim took over and did
the requested operation. So most of the code was in TCL.

Don't know if/how this could be duplicated in other simulators. YMMV.
Not a pretty solution at all, but it worked.

Regards,

Mark

[djarte]

Hi Mark,

thanks a lot for the reply. Actually i have found a pretty solution in another forum for probing but also forcing signal wires when using strings holding the hierarchical path of the wire. If you are also interested you can look at the link below. Unfortunately i do not use a Modelsim simulator so it is rather complicated for me at the moment to follow your procedure.

http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=3422

[pmvi...@gmail.com]

Hi djarte,
verificationguild is not working anymore, did not know it was offline ...
Anyway, do you mind quickly explaining what was this solution? As far as I know, it is not possible to do that as hierarchical assignments need to be resolved at compilation time? See:

https://verificationacademy.com/forums/systemverilog/how-pass-hierarchical-path-string

Pablo